Documentation/devicetree/bindings/power/mediatek,power-controller.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Mediatek Power Domains Controller
   8
   9 maintainers:
  10   - Weiyi Lu <weiyi.lu@mediatek.com>
  11   - Matthias Brugger <mbrugger@suse.com>
  12
  13 description: |
  14   Mediatek processors include support for multiple power domains which can be
  15   powered up/down by software based on different application scenes to save power.
  16
  17   IP cores belonging to a power domain should contain a 'power-domains'
  18   property that is a phandle for SCPSYS node representing the domain.
  19
  20 properties:
  21   $nodename:
  22     const: power-controller
  23
  24   compatible:
  25     enum:
  26       - mediatek,mt8167-power-controller
  27       - mediatek,mt8173-power-controller
  28       - mediatek,mt8183-power-controller
  29       - mediatek,mt8192-power-controller
  30
  31   '#power-domain-cells':
  32     const: 1
  33
  34   '#address-cells':
  35     const: 1
  36
  37   '#size-cells':
  38     const: 0
  39
  40 patternProperties:
  41   "^power-domain@[0-9a-f]+$":
  42     type: object
  43     description: |
  44       Represents the power domains within the power controller node as documented
  45       in Documentation/devicetree/bindings/power/power-domain.yaml.
  46
  47     properties:
  48
  49       '#power-domain-cells':
  50         description:
  51           Must be 0 for nodes representing a single PM domain and 1 for nodes
  52           providing multiple PM domains.
  53
  54       '#address-cells':
  55         const: 1
  56
  57       '#size-cells':
  58         const: 0
  59
  60       reg:
  61         description: |
  62           Power domain index. Valid values are defined in:
  63               "include/dt-bindings/power/mt8167-power.h" - for MT8167 type power domain.
  64               "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain.
  65               "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain.
  66               "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.
  67         maxItems: 1
  68
  69       clocks:
  70         description: |
  71           A number of phandles to clocks that need to be enabled during domain
  72           power-up sequencing.
  73
  74       clock-names:
  75         description: |
  76           List of names of clocks, in order to match the power-up sequencing
  77           for each power domain we need to group the clocks by name. BASIC
  78           clocks need to be enabled before enabling the corresponding power
  79           domain, and should not have a '-' in their name (i.e mm, mfg, venc).
  80           SUSBYS clocks need to be enabled before releasing the bus protection,
  81           and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
  82
  83           In order to follow properly the power-up sequencing, the clocks must
  84           be specified by order, adding first the BASIC clocks followed by the
  85           SUSBSYS clocks.
  86
  87       domain-supply:
  88         description: domain regulator supply.
  89
  90       mediatek,infracfg:
  91         $ref: /schemas/types.yaml#/definitions/phandle
  92         description: phandle to the device containing the INFRACFG register range.
  93
  94       mediatek,smi:
  95         $ref: /schemas/types.yaml#/definitions/phandle
  96         description: phandle to the device containing the SMI register range.
  97
  98     patternProperties:
  99       "^power-domain@[0-9a-f]+$":
 100         type: object
 101         description: |
 102           Represents a power domain child within a power domain parent node.
 103
 104         properties:
 105
 106           '#power-domain-cells':
 107             description:
 108               Must be 0 for nodes representing a single PM domain and 1 for nodes
 109               providing multiple PM domains.
 110
 111           '#address-cells':
 112             const: 1
 113
 114           '#size-cells':
 115             const: 0
 116
 117           reg:
 118             maxItems: 1
 119
 120           clocks:
 121             description: |
 122               A number of phandles to clocks that need to be enabled during domain
 123               power-up sequencing.
 124
 125           clock-names:
 126             description: |
 127               List of names of clocks, in order to match the power-up sequencing
 128               for each power domain we need to group the clocks by name. BASIC
 129               clocks need to be enabled before enabling the corresponding power
 130               domain, and should not have a '-' in their name (i.e mm, mfg, venc).
 131               SUSBYS clocks need to be enabled before releasing the bus protection,
 132               and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
 133
 134               In order to follow properly the power-up sequencing, the clocks must
 135               be specified by order, adding first the BASIC clocks followed by the
 136               SUSBSYS clocks.
 137
 138           domain-supply:
 139             description: domain regulator supply.
 140
 141           mediatek,infracfg:
 142             $ref: /schemas/types.yaml#/definitions/phandle
 143             description: phandle to the device containing the INFRACFG register range.
 144
 145           mediatek,smi:
 146             $ref: /schemas/types.yaml#/definitions/phandle
 147             description: phandle to the device containing the SMI register range.
 148
 149         patternProperties:
 150           "^power-domain@[0-9a-f]+$":
 151             type: object
 152             description: |
 153               Represents a power domain child within a power domain parent node.
 154
 155             properties:
 156
 157               '#power-domain-cells':
 158                 description:
 159                   Must be 0 for nodes representing a single PM domain and 1 for nodes
 160                   providing multiple PM domains.
 161
 162               '#address-cells':
 163                 const: 1
 164
 165               '#size-cells':
 166                 const: 0
 167
 168               reg:
 169                 maxItems: 1
 170
 171               clocks:
 172                 description: |
 173                   A number of phandles to clocks that need to be enabled during domain
 174                   power-up sequencing.
 175
 176               clock-names:
 177                 description: |
 178                   List of names of clocks, in order to match the power-up sequencing
 179                   for each power domain we need to group the clocks by name. BASIC
 180                   clocks need to be enabled before enabling the corresponding power
 181                   domain, and should not have a '-' in their name (i.e mm, mfg, venc).
 182                   SUSBYS clocks need to be enabled before releasing the bus protection,
 183                   and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
 184
 185                   In order to follow properly the power-up sequencing, the clocks must
 186                   be specified by order, adding first the BASIC clocks followed by the
 187                   SUSBSYS clocks.
 188
 189               domain-supply:
 190                 description: domain regulator supply.
 191
 192               mediatek,infracfg:
 193                 $ref: /schemas/types.yaml#/definitions/phandle
 194                 description: phandle to the device containing the INFRACFG register range.
 195
 196               mediatek,smi:
 197                 $ref: /schemas/types.yaml#/definitions/phandle
 198                 description: phandle to the device containing the SMI register range.
 199
 200             required:
 201               - reg
 202
 203             additionalProperties: false
 204
 205         required:
 206           - reg
 207
 208         additionalProperties: false
 209
 210     required:
 211       - reg
 212
 213     additionalProperties: false
 214
 215 required:
 216   - compatible
 217
 218 additionalProperties: false
 219
 220 examples:
 221   - |
 222     #include <dt-bindings/clock/mt8173-clk.h>
 223     #include <dt-bindings/power/mt8173-power.h>
 224
 225     soc {
 226         #address-cells = <2>;
 227         #size-cells = <2>;
 228
 229         scpsys: syscon@10006000 {
 230             compatible = "syscon", "simple-mfd";
 231             reg = <0 0x10006000 0 0x1000>;
 232
 233             spm: power-controller {
 234                 compatible = "mediatek,mt8173-power-controller";
 235                 #address-cells = <1>;
 236                 #size-cells = <0>;
 237                 #power-domain-cells = <1>;
 238
 239                 /* power domains of the SoC */
 240                 power-domain@MT8173_POWER_DOMAIN_VDEC {
 241                     reg = <MT8173_POWER_DOMAIN_VDEC>;
 242                     clocks = <&topckgen CLK_TOP_MM_SEL>;
 243                     clock-names = "mm";
 244                     #power-domain-cells = <0>;
 245                 };
 246                 power-domain@MT8173_POWER_DOMAIN_VENC {
 247                     reg = <MT8173_POWER_DOMAIN_VENC>;
 248                     clocks = <&topckgen CLK_TOP_MM_SEL>,
 249                              <&topckgen CLK_TOP_VENC_SEL>;
 250                     clock-names = "mm", "venc";
 251                     #power-domain-cells = <0>;
 252                 };
 253                 power-domain@MT8173_POWER_DOMAIN_ISP {
 254                     reg = <MT8173_POWER_DOMAIN_ISP>;
 255                     clocks = <&topckgen CLK_TOP_MM_SEL>;
 256                     clock-names = "mm";
 257                     #power-domain-cells = <0>;
 258                 };
 259                 power-domain@MT8173_POWER_DOMAIN_MM {
 260                     reg = <MT8173_POWER_DOMAIN_MM>;
 261                     clocks = <&topckgen CLK_TOP_MM_SEL>;
 262                     clock-names = "mm";
 263                     #power-domain-cells = <0>;
 264                     mediatek,infracfg = <&infracfg>;
 265                 };
 266                 power-domain@MT8173_POWER_DOMAIN_VENC_LT {
 267                     reg = <MT8173_POWER_DOMAIN_VENC_LT>;
 268                     clocks = <&topckgen CLK_TOP_MM_SEL>,
 269                              <&topckgen CLK_TOP_VENC_LT_SEL>;
 270                     clock-names = "mm", "venclt";
 271                     #power-domain-cells = <0>;
 272                 };
 273                 power-domain@MT8173_POWER_DOMAIN_AUDIO {
 274                     reg = <MT8173_POWER_DOMAIN_AUDIO>;
 275                     #power-domain-cells = <0>;
 276                 };
 277                 power-domain@MT8173_POWER_DOMAIN_USB {
 278                     reg = <MT8173_POWER_DOMAIN_USB>;
 279                     #power-domain-cells = <0>;
 280                 };
 281                 power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
 282                     reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
 283                     clocks = <&clk26m>;
 284                     clock-names = "mfg";
 285                     #address-cells = <1>;
 286                     #size-cells = <0>;
 287                     #power-domain-cells = <1>;
 288
 289                     power-domain@MT8173_POWER_DOMAIN_MFG_2D {
 290                         reg = <MT8173_POWER_DOMAIN_MFG_2D>;
 291                         #address-cells = <1>;
 292                         #size-cells = <0>;
 293                         #power-domain-cells = <1>;
 294
 295                         power-domain@MT8173_POWER_DOMAIN_MFG {
 296                             reg = <MT8173_POWER_DOMAIN_MFG>;
 297                             #power-domain-cells = <0>;
 298                             mediatek,infracfg = <&infracfg>;
 299                         };
 300                     };
 301                 };
 302             };
 303         };
 304     };