1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 # Copyright (C) STMicroelectronics 2019.
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: STM32 GPIO and Pin Mux/Config controller
11 - Alexandre TORGUE <alexandre.torgue@st.com>
14 STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
15 controller. It controls the input/output settings on the available pins and
16 also provides ability to multiplex and configure the output of various
17 on-chip controllers onto these pads.
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
24 - st,stm32f746-pinctrl
25 - st,stm32f769-pinctrl
26 - st,stm32h743-pinctrl
27 - st,stm32mp157-pinctrl
28 - st,stm32mp157-z-pinctrl
36 pins-are-numbered: true
41 - $ref: "/schemas/types.yaml#/definitions/phandle-array"
42 description: Should be phandle/offset/mask
44 - description: Phandle to the syscon node which includes IRQ mux selection.
45 - description: The offset of the IRQ mux selection register.
46 - description: The field mask of IRQ mux, needed if different of 0xf.
50 - $ref: /schemas/types.yaml#/definitions/uint32
53 Indicates the SOC package used.
54 More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
77 Number of available gpios in a bank.
83 - $ref: "/schemas/types.yaml#/definitions/string"
98 Should be a name string for this bank as specified in the datasheet.
102 - $ref: "/schemas/types.yaml#/definitions/uint32"
107 Should correspond to the EXTI IOport selection (EXTI line used
108 to select GPIOs as interrupts).
123 A pinctrl node should contain at least one subnode representing the
124 pinctrl group available on the machine. Each subnode will list the
125 pins it needs, and how they should be configured, with regard to muxer
126 configuration, pullups, drive, output high/low and output speed.
130 - $ref: "/schemas/types.yaml#/definitions/uint32-array"
132 Integer array, represents gpio pin number and mux setting.
133 Supported pin number and mux varies for different SoCs, and are
134 defined in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
135 These defines are calculated as: ((port * 16 + line) << 8) | function
137 - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
138 - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
139 - function: The function number, can be:
141 * 1 : Alternate Function 0
142 * 2 : Alternate Function 1
143 * 3 : Alternate Function 2
145 * 16 : Alternate Function 15
147 To simplify the usage, macro is available to generate "pinmux" field.
148 This macro is available here:
149 - include/dt-bindings/pinctrl/stm32-pinfunc.h
150 Some examples of using macro:
151 /* GPIO A9 set as alernate function 2 */
153 pinmux = <STM32_PINMUX('A', 9, AF2)>;
155 /* GPIO A9 set as GPIO */
157 pinmux = <STM32_PINMUX('A', 9, GPIO)>;
159 /* GPIO A9 set as analog */
161 pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
185 - $ref: /schemas/types.yaml#/definitions/uint32
200 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
201 #include <dt-bindings/mfd/stm32f4-rcc.h>
204 #address-cells = <1>;
206 compatible = "st,stm32f429-pinctrl";
207 ranges = <0 0x40020000 0x3000>;
214 resets = <&reset_ahb1 0>;
215 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
216 st,bank-name = "GPIOA";
220 //Example 2 (using gpio-ranges)
222 #address-cells = <1>;
224 compatible = "st,stm32f429-pinctrl";
225 ranges = <0 0x50020000 0x3000>;
231 reg = <0x1000 0x400>;
232 resets = <&reset_ahb1 0>;
233 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
234 st,bank-name = "GPIOB";
235 gpio-ranges = <&pinctrl 0 0 16>;
241 reg = <0x2000 0x400>;
242 resets = <&reset_ahb1 0>;
243 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
244 st,bank-name = "GPIOC";
246 gpio-ranges = <&pinctrl 0 16 3>,
251 //Example 3 pin groups
253 usart1_pins_a: usart1-0 {
255 pinmux = <STM32_PINMUX('A', 9, AF7)>;
261 pinmux = <STM32_PINMUX('A', 10, AF7)>;
268 pinctrl-0 = <&usart1_pins_a>;
269 pinctrl-names = "default";