1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 # Copyright (C) STMicroelectronics 2019.
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: STM32 GPIO and Pin Mux/Config controller
11 - Alexandre TORGUE <alexandre.torgue@st.com>
14 STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
15 controller. It controls the input/output settings on the available pins and
16 also provides ability to multiplex and configure the output of various
17 on-chip controllers onto these pads.
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
24 - st,stm32f746-pinctrl
25 - st,stm32f769-pinctrl
26 - st,stm32h743-pinctrl
27 - st,stm32mp157-pinctrl
28 - st,stm32mp157-z-pinctrl
36 pins-are-numbered: true
40 $ref: "/schemas/types.yaml#/definitions/phandle-array"
41 description: Should be phandle/offset/mask
43 - description: Phandle to the syscon node which includes IRQ mux selection.
44 - description: The offset of the IRQ mux selection register.
45 - description: The field mask of IRQ mux, needed if different of 0xf.
49 - $ref: /schemas/types.yaml#/definitions/uint32
52 Indicates the SOC package used.
53 More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
76 Number of available gpios in a bank.
82 - $ref: "/schemas/types.yaml#/definitions/string"
97 Should be a name string for this bank as specified in the datasheet.
101 - $ref: "/schemas/types.yaml#/definitions/uint32"
106 Should correspond to the EXTI IOport selection (EXTI line used
107 to select GPIOs as interrupts).
122 A pinctrl node should contain at least one subnode representing the
123 pinctrl group available on the machine. Each subnode will list the
124 pins it needs, and how they should be configured, with regard to muxer
125 configuration, pullups, drive, output high/low and output speed.
129 - $ref: "/schemas/types.yaml#/definitions/uint32-array"
131 Integer array, represents gpio pin number and mux setting.
132 Supported pin number and mux varies for different SoCs, and are
133 defined in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
134 These defines are calculated as: ((port * 16 + line) << 8) | function
136 - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
137 - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
138 - function: The function number, can be:
140 * 1 : Alternate Function 0
141 * 2 : Alternate Function 1
142 * 3 : Alternate Function 2
144 * 16 : Alternate Function 15
146 To simplify the usage, macro is available to generate "pinmux" field.
147 This macro is available here:
148 - include/dt-bindings/pinctrl/stm32-pinfunc.h
149 Some examples of using macro:
150 /* GPIO A9 set as alernate function 2 */
152 pinmux = <STM32_PINMUX('A', 9, AF2)>;
154 /* GPIO A9 set as GPIO */
156 pinmux = <STM32_PINMUX('A', 9, GPIO)>;
158 /* GPIO A9 set as analog */
160 pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
184 - $ref: /schemas/types.yaml#/definitions/uint32
199 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
202 #address-cells = <1>;
204 compatible = "st,stm32f429-pinctrl";
205 ranges = <0 0x40020000 0x3000>;
212 resets = <&reset_ahb1 0>;
213 st,bank-name = "GPIOA";
217 //Example 2 (using gpio-ranges)
219 #address-cells = <1>;
221 compatible = "st,stm32f429-pinctrl";
222 ranges = <0 0x50020000 0x3000>;
228 reg = <0x1000 0x400>;
229 resets = <&reset_ahb1 0>;
230 st,bank-name = "GPIOB";
231 gpio-ranges = <&pinctrl 0 0 16>;
237 reg = <0x2000 0x400>;
238 resets = <&reset_ahb1 0>;
239 st,bank-name = "GPIOC";
241 gpio-ranges = <&pinctrl 0 16 3>,
246 //Example 3 pin groups
248 usart1_pins_a: usart1-0 {
250 pinmux = <STM32_PINMUX('A', 9, AF7)>;
256 pinmux = <STM32_PINMUX('A', 10, AF7)>;
263 pinctrl-0 = <&usart1_pins_a>;
264 pinctrl-names = "default";