1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/{G2L,V2L} combined Pin and GPIO controller
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
14 The Renesas SoCs of the RZ/{G2L,V2L} alike series feature a combined Pin and
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
17 Each port features up to 8 pins, each of them configurable for GPIO function
18 (port mode) or in alternate function mode.
19 Up to 8 different alternate function modes exist for each single pin.
26 - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2}
27 - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
31 - renesas,r9a07g054-pinctrl # RZ/V2L
32 - const: renesas,r9a07g044-pinctrl # RZ/G2{L,LC} fallback for RZ/V2L
42 The first cell contains the global GPIO port index, constructed using the
43 RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the
44 second cell represents consumer flag as mentioned in ../gpio/gpio.txt
45 E.g. "RZG2L_GPIO(39, 1)" for P39_1.
58 - description: GPIO_RSTN signal
59 - description: GPIO_PORT_RESETN signal
60 - description: GPIO_SPARE_RESETN signal
66 - $ref: pincfg-node.yaml#
67 - $ref: pinmux-node.yaml#
70 Pin controller client devices use pin configuration subnodes (children
71 and grandchildren) for desired pin configuration.
72 Client device subnodes use below standard properties.
78 Values are constructed from GPIO port number, pin number, and
79 alternate function configuration number using the RZG2L_PORT_PINMUX()
80 helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h>.
84 output-impedance-ohms:
85 enum: [ 33, 50, 66, 100 ]
87 description: I/O voltage in millivolt.
88 enum: [ 1800, 2500, 3300 ]
101 additionalProperties:
102 $ref: "#/additionalProperties/anyOf/0"
105 - $ref: "pinctrl.yaml#"
119 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
120 #include <dt-bindings/clock/r9a07g044-cpg.h>
122 pinctrl: pinctrl@11030000 {
123 compatible = "renesas,r9a07g044-pinctrl";
124 reg = <0x11030000 0x10000>;
128 gpio-ranges = <&pinctrl 0 0 392>;
129 clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
130 resets = <&cpg R9A07G044_GPIO_RSTN>,
131 <&cpg R9A07G044_GPIO_PORT_RESETN>,
132 <&cpg R9A07G044_GPIO_SPARE_RESETN>;
133 power-domains = <&cpg>;
135 scif0_pins: serial0 {
136 pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* Tx */
137 <RZG2L_PORT_PINMUX(38, 1, 1)>; /* Rx */
141 pins = "RIIC1_SDA", "RIIC1_SCL";
147 gpios = <RZG2L_GPIO(39, 2) 0>;
149 line-name = "sd1_pwr_en";
154 pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>, /* CD */
155 <RZG2L_PORT_PINMUX(19, 1, 1)>; /* WP */
156 power-source = <3300>;
160 pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
161 power-source = <3300>;
165 pins = "SD1_CLK", "SD1_CMD";
166 power-source = <3300>;