Documentation/devicetree/bindings/pinctrl/qcom,sm6350-pinctrl.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm6350-pinctrl.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Technologies, Inc. SM6350 TLMM block
   8
   9 maintainers:
  10   - Konrad Dybcio <konrad.dybcio@somainline.org>
  11
  12 description: |
  13   This binding describes the Top Level Mode Multiplexer (TLMM) block found
  14   in the SM6350 platform.
  15
  16 allOf:
  17   - $ref: "pinctrl.yaml#"
  18   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
  19
  20 properties:
  21   compatible:
  22     const: qcom,sm6350-tlmm
  23
  24   reg:
  25     maxItems: 1
  26
  27   interrupts: true
  28   interrupt-controller: true
  29   '#interrupt-cells': true
  30   gpio-controller: true
  31   gpio-reserved-ranges: true
  32   '#gpio-cells': true
  33   gpio-ranges: true
  34   wakeup-parent: true
  35
  36 required:
  37   - compatible
  38   - reg
  39
  40 additionalProperties: false
  41
  42 patternProperties:
  43   '-state$':
  44     oneOf:
  45       - $ref: "#/$defs/qcom-sm6350-tlmm-state"
  46       - patternProperties:
  47           ".*":
  48             $ref: "#/$defs/qcom-sm6350-tlmm-state"
  49
  50 $defs:
  51   qcom-sm6350-tlmm-state:
  52     type: object
  53     description:
  54       Pinctrl node's client devices use subnodes for desired pin configuration.
  55       Client device subnodes use below standard properties.
  56     $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
  57
  58     properties:
  59       pins:
  60         description:
  61           List of gpio pins affected by the properties specified in this
  62           subnode.
  63         items:
  64           oneOf:
  65             - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-7])$"
  66             - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
  67         minItems: 1
  68         maxItems: 36
  69
  70       function:
  71         description:
  72           Specify the alternative function to be configured for the specified
  73           pins.
  74
  75         enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1, atest_char2,
  76                 atest_char3, atest_tsens, atest_tsens2, atest_usb1, atest_usb10, atest_usb11,
  77                 atest_usb12, atest_usb13, atest_usb2, atest_usb20, atest_usb21, atest_usb22,
  78                 atest_usb23, audio_ref, btfm_slimbus, cam_mclk0, cam_mclk1, cam_mclk2, cam_mclk3,
  79                 cam_mclk4, cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3,
  80                 cci_timer4, cri_trng, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3,
  81                 dp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gp_pdm0, gp_pdm1, gp_pdm2, gpio,
  82                 gps_tx, ibi_i3c, jitter_bist, ldo_en, ldo_update, lpass_ext, m_voc, mclk,
  83                 mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s_0, mi2s_1, mi2s_2,
  84                 mss_lte, nav_gpio, nav_pps, pa_indicator, pcie0_clk, phase_flag0, phase_flag1,
  85                 phase_flag10, phase_flag11, phase_flag12, phase_flag13, phase_flag14, phase_flag15,
  86                 phase_flag16, phase_flag17, phase_flag18, phase_flag19, phase_flag2, phase_flag20,
  87                 phase_flag21, phase_flag22, phase_flag23, phase_flag24, phase_flag25, phase_flag26,
  88                 phase_flag27, phase_flag28, phase_flag29, phase_flag3, phase_flag30, phase_flag31,
  89                 phase_flag4, phase_flag5, phase_flag6, phase_flag7, phase_flag8, phase_flag9,
  90                 pll_bist, pll_bypassnl, pll_reset, prng_rosc, qdss_cti, qdss_gpio, qdss_gpio0,
  91                 qdss_gpio1, qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14,
  92                 qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6,
  93                 qdss_gpio7, qdss_gpio8, qdss_gpio9, qlink0_enable, qlink0_request, qlink0_wmss,
  94                 qlink1_enable, qlink1_request, qlink1_wmss, qup00, qup01, qup02, qup10, qup11,
  95                 qup12, qup13_f1, qup13_f2, qup14, rffe0_clk, rffe0_data, rffe1_clk, rffe1_data,
  96                 rffe2_clk, rffe2_data, rffe3_clk, rffe3_data, rffe4_clk, rffe4_data, sd_write,
  97                 sdc1_tb, sdc2_tb, sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1,
  98                 tsense_pwm2, uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data,
  99                 uim2_present, uim2_reset, usb_phy, vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1,
 100                 wlan2_adc0, wlan2_adc1, ]
 101
 102
 103       bias-disable: true
 104       bias-pull-down: true
 105       bias-pull-up: true
 106       drive-strength: true
 107       input-enable: true
 108       output-high: true
 109       output-low: true
 110
 111     required:
 112       - pins
 113       - function
 114
 115     additionalProperties: false
 116
 117 examples:
 118   - |
 119         #include <dt-bindings/interrupt-controller/arm-gic.h>
 120         pinctrl@f100000 {
 121                 compatible = "qcom,sm6350-tlmm";
 122                 reg = <0x0f100000 0x300000>;
 123                 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 124                 gpio-controller;
 125                 #gpio-cells = <2>;
 126                 interrupt-controller;
 127                 #interrupt-cells = <2>;
 128                 gpio-ranges = <&tlmm 0 0 157>;
 129
 130                 gpio-wo-subnode-state {
 131                         pins = "gpio1";
 132                         function = "gpio";
 133                 };
 134
 135                 uart-w-subnodes-state {
 136                         rx {
 137                                 pins = "gpio25";
 138                                 function = "qup13_f2";
 139                                 bias-disable;
 140                         };
 141
 142                         tx {
 143                                 pins = "gpio26";
 144                                 function = "qup13_f2";
 145                                 bias-disable;
 146                         };
 147                 };
 148         };
 149 ...