Documentation/devicetree/bindings/pinctrl/qcom,sdx75-tlmm.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/qcom,sdx75-tlmm.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Technologies, Inc. SDX75 TLMM block
   8
   9 maintainers:
  10   - Rohit Agarwal <quic_rohiagar@quicinc.com>
  11
  12 description:
  13   Top Level Mode Multiplexer pin controller in Qualcomm SDX75 SoC.
  14
  15 allOf:
  16   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
  17
  18 properties:
  19   compatible:
  20     const: qcom,sdx75-tlmm
  21
  22   reg:
  23     maxItems: 1
  24
  25   interrupts:
  26     maxItems: 1
  27
  28   gpio-reserved-ranges:
  29     minItems: 1
  30     maxItems: 67
  31
  32   gpio-line-names:
  33     maxItems: 133
  34
  35 patternProperties:
  36   "-state$":
  37     oneOf:
  38       - $ref: "#/$defs/qcom-sdx75-tlmm-state"
  39       - patternProperties:
  40           "-pins$":
  41             $ref: "#/$defs/qcom-sdx75-tlmm-state"
  42         additionalProperties: false
  43
  44 $defs:
  45   qcom-sdx75-tlmm-state:
  46     type: object
  47     description:
  48       Pinctrl node's client devices use subnodes for desired pin configuration.
  49       Client device subnodes use below standard properties.
  50     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
  51     unevaluatedProperties: false
  52
  53     properties:
  54       pins:
  55         description:
  56           List of gpio pins affected by the properties specified in this
  57           subnode.
  58         items:
  59           oneOf:
  60             - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2])$"
  61             - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk, sdc2_cmd, sdc2_data ]
  62         minItems: 1
  63         maxItems: 36
  64
  65       function:
  66         description:
  67           Specify the alternative function to be configured for the specified
  68           pins.
  69         enum: [ adsp_ext, atest_char, audio_ref_clk, bimc_dte, char_exec, coex_uart2,
  70                 coex_uart, cri_trng, cri_trng0, cri_trng1, dbg_out_clk, ddr_bist,
  71                 ddr_pxi0, ebi0_wrcdc, ebi2_a, ebi2_lcd, ebi2_lcd_te, emac0_mcg,
  72                 emac0_ptp, emac1_mcg, emac1_ptp, emac_cdc, emac_pps_in, eth0_mdc,
  73                 eth0_mdio, eth1_mdc, eth1_mdio, ext_dbg, gcc_125_clk, gcc_gp1_clk,
  74                 gcc_gp2_clk, gcc_gp3_clk, gcc_plltest, gpio, i2s_mclk, jitter_bist,
  75                 ldo_en, ldo_update, m_voc, mgpi_clk, native_char, native_tsens,
  76                 native_tsense, nav_dr_sync, nav_gpio, pa_indicator, pci_e,
  77                 pcie0_clkreq_n, pcie1_clkreq_n, pcie2_clkreq_n, pll_bist_sync,
  78                 pll_clk_aux, pll_ref_clk, pri_mi2s, prng_rosc, qdss_cti, qdss_gpio,
  79                 qlink0_b_en, qlink0_b_req, qlink0_l_en, qlink0_l_req, qlink0_wmss,
  80                 qlink1_l_en, qlink1_l_req, qlink1_wmss, qup_se0, qup_se1_l2_mira,
  81                 qup_se1_l2_mirb, qup_se1_l3_mira, qup_se1_l3_mirb, qup_se2, qup_se3,
  82                 qup_se4, qup_se5, qup_se6, qup_se7, qup_se8, rgmii_rx_ctl, rgmii_rxc,
  83                 rgmii_rxd, rgmii_tx_ctl, rgmii_txc, rgmii_txd, sd_card, sdc1_tb,
  84                 sdc2_tb_trig, sec_mi2s, sgmii_phy_intr0_n, sgmii_phy_intr1_n,
  85                 spmi_coex, spmi_vgi, tgu_ch0_trigout, tmess_prng0, tmess_prng1,
  86                 tmess_prng2, tmess_prng3, tri_mi2s, uim1_clk, uim1_data, uim1_present,
  87                 uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,
  88                 usb2phy_ac_en, vsense_trigger_mirnat]
  89
  90     required:
  91       - pins
  92
  93 required:
  94   - compatible
  95   - reg
  96
  97 unevaluatedProperties: false
  98
  99 examples:
 100   - |
 101     #include <dt-bindings/interrupt-controller/arm-gic.h>
 102     tlmm: pinctrl@f100000 {
 103         compatible = "qcom,sdx75-tlmm";
 104         reg = <0x0f100000 0x300000>;
 105         gpio-controller;
 106         #gpio-cells = <2>;
 107         gpio-ranges = <&tlmm 0 0 133>;
 108         interrupt-controller;
 109         #interrupt-cells = <2>;
 110         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 111
 112         gpio-wo-state {
 113             pins = "gpio1";
 114             function = "gpio";
 115         };
 116
 117         uart-w-state {
 118             rx-pins {
 119                 pins = "gpio12";
 120                 function = "qup_se1_l2_mira";
 121                 bias-disable;
 122             };
 123
 124             tx-pins {
 125                 pins = "gpio13";
 126                 function = "qup_se1_l3_mira";
 127                 bias-disable;
 128             };
 129         };
 130     };
 131 ...