Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/qcom,sdx55-pinctrl.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Technologies, Inc. SDX55 TLMM block
   8
   9 maintainers:
  10   - Vinod Koul <vkoul@kernel.org>
  11
  12 description:
  13   Top Level Mode Multiplexer pin controller in Qualcomm SDX55 SoC.
  14
  15 properties:
  16   compatible:
  17     const: qcom,sdx55-pinctrl
  18
  19   reg:
  20     description: Specifies the base address and size of the TLMM register space
  21     maxItems: 1
  22
  23   interrupts:
  24     maxItems: 1
  25
  26   interrupt-controller: true
  27   "#interrupt-cells": true
  28   gpio-controller: true
  29   "#gpio-cells": true
  30   gpio-ranges: true
  31
  32   gpio-reserved-ranges:
  33     maxItems: 1
  34
  35 patternProperties:
  36   "-state$":
  37     oneOf:
  38       - $ref: "#/$defs/qcom-sdx55-tlmm-state"
  39       - patternProperties:
  40           "-pins$":
  41             $ref: "#/$defs/qcom-sdx55-tlmm-state"
  42         additionalProperties: false
  43
  44 $defs:
  45   qcom-sdx55-tlmm-state:
  46     type: object
  47     description:
  48       Pinctrl node's client devices use subnodes for desired pin configuration.
  49       Client device subnodes use below standard properties.
  50     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
  51     unevaluatedProperties: false
  52
  53     properties:
  54       pins:
  55         description:
  56           List of gpio pins affected by the properties specified in this subnode.
  57         items:
  58           oneOf:
  59             - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-7])$"
  60             - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
  61         minItems: 1
  62         maxItems: 36
  63
  64       function:
  65         description:
  66           Specify the alternative function to be configured for the specified
  67           pins. Functions are only valid for gpio pins.
  68         enum: [ adsp_ext, atest, audio_ref, bimc_dte0, bimc_dte1, blsp_i2c1,
  69                 blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_spi1, blsp_spi2,
  70                 blsp_spi3, blsp_spi4, blsp_uart1, blsp_uart2, blsp_uart3,
  71                 blsp_uart4, char_exec, coex_uart, coex_uart2, cri_trng,
  72                 cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
  73                 ebi0_wrcdc, ebi2_a, ebi2_lcd, emac_gcc0, emac_gcc1,
  74                 emac_pps0, emac_pps1, ext_dbg, gcc_gp1, gcc_gp2, gcc_gp3,
  75                 gcc_plltest, gpio, i2s_mclk, jitter_bist, ldo_en, ldo_update,
  76                 mgpi_clk, m_voc, native_char, native_char0, native_char1,
  77                 native_char2, native_char3, native_tsens, native_tsense,
  78                 nav_gpio, pa_indicator, pcie_clkreq, pci_e, pll_bist, pll_ref,
  79                 pll_test, pri_mi2s, prng_rosc, qdss_cti, qdss_gpio,
  80                 qdss_gpio0, qdss_gpio1, qdss_gpio2, qdss_gpio3, qdss_gpio4,
  81                 qdss_gpio5, qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9,
  82                 qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13,
  83                 qdss_gpio14, qdss_gpio15, qdss_stm0, qdss_stm1, qdss_stm2,
  84                 qdss_stm3, qdss_stm4, qdss_stm5, qdss_stm6, qdss_stm7,
  85                 qdss_stm8, qdss_stm9, qdss_stm10, qdss_stm11, qdss_stm12,
  86                 qdss_stm13, qdss_stm14, qdss_stm15, qdss_stm16, qdss_stm17,
  87                 qdss_stm18, qdss_stm19, qdss_stm20, qdss_stm21, qdss_stm22,
  88                 qdss_stm23, qdss_stm24, qdss_stm25, qdss_stm26, qdss_stm27,
  89                 qdss_stm28, qdss_stm29, qdss_stm30, qdss_stm31, qlink0_en,
  90                 qlink0_req, qlink0_wmss, qlink1_en, qlink1_req, qlink1_wmss,
  91                 spmi_coex, sec_mi2s, spmi_vgi, tgu_ch0, uim1_clk, uim1_data,
  92                 uim1_present, uim1_reset, uim2_clk, uim2_data, uim2_present,
  93                 uim2_reset, usb2phy_ac, vsense_trigger ]
  94
  95     required:
  96       - pins
  97
  98 allOf:
  99   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
 100
 101 required:
 102   - compatible
 103   - reg
 104
 105 additionalProperties: false
 106
 107 examples:
 108   - |
 109     #include <dt-bindings/interrupt-controller/arm-gic.h>
 110     tlmm: pinctrl@1f00000 {
 111         compatible = "qcom,sdx55-pinctrl";
 112         reg = <0x0f100000 0x300000>;
 113         gpio-controller;
 114         #gpio-cells = <2>;
 115         gpio-ranges = <&tlmm 0 0 108>;
 116         interrupt-controller;
 117         #interrupt-cells = <2>;
 118         interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
 119
 120         serial-state {
 121             pins = "gpio8", "gpio9";
 122             function = "blsp_uart3";
 123             drive-strength = <8>;
 124             bias-disable;
 125         };
 126     };
 127
 128 ...