Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-pinctrl.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Technologies, Inc. SC7280 TLMM block
   8
   9 maintainers:
  10   - Bjorn Andersson <andersson@kernel.org>
  11
  12 description:
  13   Top Level Mode Multiplexer pin controller in Qualcomm SC7280 SoC.
  14
  15 properties:
  16   compatible:
  17     const: qcom,sc7280-pinctrl
  18
  19   reg:
  20     maxItems: 1
  21
  22   interrupts:
  23     description: Specifies the TLMM summary IRQ
  24     maxItems: 1
  25
  26   gpio-reserved-ranges:
  27     minItems: 1
  28     maxItems: 88
  29
  30   gpio-line-names:
  31     maxItems: 175
  32
  33 patternProperties:
  34   "-state$":
  35     oneOf:
  36       - $ref: "#/$defs/qcom-sc7280-tlmm-state"
  37       - patternProperties:
  38           "-pins$":
  39             $ref: "#/$defs/qcom-sc7280-tlmm-state"
  40         additionalProperties: false
  41
  42 $defs:
  43   qcom-sc7280-tlmm-state:
  44     type: object
  45     description:
  46       Pinctrl node's client devices use subnodes for desired pin configuration.
  47       Client device subnodes use below standard properties.
  48     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
  49     unevaluatedProperties: false
  50
  51     properties:
  52       pins:
  53         description:
  54           List of gpio pins affected by the properties specified in this
  55           subnode.
  56         items:
  57           oneOf:
  58             - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-4])$"
  59             - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
  60                       sdc2_cmd, sdc2_data, ufs_reset ]
  61         minItems: 1
  62         maxItems: 16
  63
  64       function:
  65         description:
  66           Specify the alternative function to be configured for the specified
  67           pins.
  68
  69         enum: [ atest_char, atest_char0, atest_char1, atest_char2,
  70                 atest_char3, atest_usb0, atest_usb00, atest_usb01,
  71                 atest_usb02, atest_usb03, atest_usb1, atest_usb10,
  72                 atest_usb11, atest_usb12, atest_usb13, audio_ref,
  73                 cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1,
  74                 cci_timer2, cci_timer3, cci_timer4, cmu_rng0, cmu_rng1,
  75                 cmu_rng2, cmu_rng3, coex_uart1, cri_trng, cri_trng0,
  76                 cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, dp_hot,
  77                 dp_lcd, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3,
  78                 gpio, host2wlan_sol, ibi_i3c, jitter_bist, lpass_slimbus,
  79                 mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3,
  80                 mdp_vsync4, mdp_vsync5, mi2s0_data0, mi2s0_data1, mi2s0_sck,
  81                 mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws,
  82                 mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, mss_grfc0,
  83                 mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12, mss_grfc2,
  84                 mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6, mss_grfc7,
  85                 mss_grfc8, mss_grfc9, nav_gpio0, nav_gpio1, nav_gpio2,
  86                 pa_indicator, pcie0_clkreqn, pcie1_clkreqn, phase_flag,
  87                 pll_bist, pll_bypassnl, pll_clk, pll_reset, pri_mi2s, prng_rosc,
  88                 qdss, qdss_cti, qlink0_enable, qlink0_request, qlink0_wmss,
  89                 qlink1_enable, qlink1_request, qlink1_wmss, qspi_clk, qspi_cs,
  90                 qspi_data, qup00, qup01, qup02, qup03, qup04, qup05, qup06, qup07,
  91                 qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17,
  92                 sdc40, sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, sd_write,
  93                 sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tsense_pwm1,
  94                 tsense_pwm2, uim0_clk, uim0_data, uim0_present, uim0_reset,
  95                 uim1_clk, uim1_data, uim1_present, uim1_reset, usb2phy_ac,
  96                 usb_phy, vfr_0, vfr_1, vsense_trigger ]
  97
  98     required:
  99       - pins
 100
 101 allOf:
 102   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
 103
 104 required:
 105   - compatible
 106   - reg
 107
 108 unevaluatedProperties: false
 109
 110 examples:
 111   - |
 112     #include <dt-bindings/interrupt-controller/arm-gic.h>
 113     tlmm: pinctrl@f000000 {
 114         compatible = "qcom,sc7280-pinctrl";
 115         reg = <0xf000000 0x1000000>;
 116         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 117         gpio-controller;
 118         #gpio-cells = <2>;
 119         interrupt-controller;
 120         #interrupt-cells = <2>;
 121         gpio-ranges = <&tlmm 0 0 175>;
 122         wakeup-parent = <&pdc>;
 123
 124         qup_uart5_default: qup-uart5-state {
 125             pins = "gpio46", "gpio47";
 126             function = "qup13";
 127             drive-strength = <2>;
 128             bias-disable;
 129         };
 130     };