1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pinctrl/qcom,msm8974-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm MSM8974 TLMM pin controller
10 - Bjorn Andersson <andersson@kernel.org>
11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
14 Top Level Mode Multiplexer pin controller in Qualcomm MSM8974 SoC.
18 const: qcom,msm8974-pinctrl
26 interrupt-controller: true
27 "#interrupt-cells": true
43 - $ref: "#/$defs/qcom-msm8974-tlmm-state"
46 $ref: "#/$defs/qcom-msm8974-tlmm-state"
47 additionalProperties: false
50 qcom-msm8974-tlmm-state:
53 Pinctrl node's client devices use subnodes for desired pin configuration.
54 Client device subnodes use below standard properties.
55 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
56 unevaluatedProperties: false
61 List of gpio pins affected by the properties specified in this
65 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-5])$"
66 - enum: [ hsic_data, hsic_strobe, sdc1_clk, sdc1_cmd, sdc1_data,
67 sdc2_clk, sdc2_cmd, sdc2_data ]
73 Specify the alternative function to be configured for the specified
76 enum: [ gpio, cci_i2c0, cci_i2c1, uim1, uim2, uim_batt_alarm,
77 blsp_uim1, blsp_uart1, blsp_i2c1, blsp_spi1, blsp_uim2,
78 blsp_uart2, blsp_i2c2, blsp_spi2, blsp_uim3, blsp_uart3,
79 blsp_i2c3, blsp_spi3, blsp_uim4, blsp_uart4, blsp_i2c4,
80 blsp_spi4, blsp_uim5, blsp_uart5, blsp_i2c5, blsp_spi5,
81 blsp_uim6, blsp_uart6, blsp_i2c6, blsp_spi6, blsp_uim7,
82 blsp_uart7, blsp_i2c7, blsp_spi7, blsp_uim8, blsp_uart8,
83 blsp_i2c8, blsp_spi8, blsp_uim9, blsp_uart9, blsp_i2c9,
84 blsp_spi9, blsp_uim10, blsp_uart10, blsp_i2c10, blsp_spi10,
85 blsp_uim11, blsp_uart11, blsp_i2c11, blsp_spi11, blsp_uim12,
86 blsp_uart12, blsp_i2c12, blsp_spi12, blsp_spi1_cs1,
87 blsp_spi2_cs2, blsp_spi_cs3, blsp_spi2_cs1, blsp_spi2_cs2
88 blsp_spi2_cs3, blsp_spi10_cs1, blsp_spi10_cs2, blsp_spi10_cs3,
89 sdc3, sdc4, gcc_gp_clk1, gcc_gp_clk2, gcc_gp_clk3, cci_timer0,
90 cci_timer1, cci_timer2, cci_timer3, cci_async_in0,
91 cci_async_in1, cci_async_in2, cam_mckl0, cam_mclk1, cam_mclk2,
92 cam_mclk3, mdp_vsync, hdmi_cec, hdmi_ddc, hdmi_hpd, edp_hpd,
93 gp_pdm0, gp_pdm1, gp_pdm2, gp_pdm3, gp0_clk, gp1_clk, gp_mn,
94 tsif1, tsif2, hsic, grfc, audio_ref_clk, qua_mi2s, pri_mi2s,
95 spkr_mi2s, ter_mi2s, sec_mi2s, bt, fm, wlan, slimbus, hsic_ctl ]
112 bias-pull-down: false
115 drive-strength: false
121 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
127 additionalProperties: false
131 #include <dt-bindings/interrupt-controller/arm-gic.h>
132 tlmm: pinctrl@fd510000 {
133 compatible = "qcom,msm8974-pinctrl";
134 reg = <0xfd510000 0x4000>;
136 gpio-ranges = <&tlmm 0 0 146>;
138 interrupt-controller;
139 #interrupt-cells = <2>;
140 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
146 drive-strength = <2>;
152 drive-strength = <2>;
158 drive-strength = <2>;
162 blsp2-uart1-sleep-state {
163 pins = "gpio41", "gpio42", "gpio43", "gpio44";
165 drive-strength = <2>;
170 pins = "hsic_data", "hsic_strobe";