1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8195.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek MT8195 Pin Controller
10 - Sean Wang <sean.wang@mediatek.com>
13 The Mediatek's Pin controller is used to control SoC pins.
17 const: mediatek,mt8195-pinctrl
23 Number of cells in GPIO specifier. Since the generic GPIO binding is used,
24 the amount of cells must be specified as 2. See the below
25 mentioned gpio binding representation for description of particular cells.
29 description: gpio valid number range.
34 Physical address base for gpio base registers. There are 8 GPIO
35 physical address base in mt8195.
40 Gpio base register names.
43 interrupt-controller: true
49 description: The interrupt outputs to sysirq.
52 #PIN CONFIGURATION NODES
57 A pinctrl node should contain at least one subnodes representing the
58 pinctrl groups available on the machine. Each subnode will list the
59 pins it needs, and how they should be configured, with regard to muxer
60 configuration, pullups, drive strength, input enable/disable and
62 An example of using macro:
64 /* GPIO0 set as multifunction GPIO0 */
66 pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
68 /* GPIO8 set as multifunction SDA0 */
70 pinmux = <PINMUX_GPIO8__FUNC_SDA0>;
73 $ref: "pinmux-node.yaml"
78 Integer array, represents gpio pin number and mux setting.
79 Supported pin number and mux varies for different SoCs, and are defined
80 as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
84 It can support some arguments which is from 0 to 7. It can only support
85 2/4/6/8/10/12/14/16mA in mt8195.
86 enum: [0, 1, 2, 3, 4, 5, 6, 7]
102 input-schmitt-enable: true
104 input-schmitt-disable: true
109 additionalProperties: false
115 - interrupt-controller
121 additionalProperties: false
125 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
126 #include <dt-bindings/interrupt-controller/arm-gic.h>
127 pio: pinctrl@10005000 {
128 compatible = "mediatek,mt8195-pinctrl";
129 reg = <0x10005000 0x1000>,
137 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
138 "iocfg_br", "iocfg_lm", "iocfg_rb",
142 gpio-ranges = <&pio 0 0 144>;
143 interrupt-controller;
144 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH 0>;
145 #interrupt-cells = <2>;
148 pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;