1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6797-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek MT6797 Pin Controller Device Tree Bindings
10 - Sean Wang <sean.wang@kernel.org>
13 The MediaTek's MT6797 Pin controller is used to control SoC pins.
17 const: mediatek,mt6797-pinctrl
36 Number of cells in GPIO specifier. Since the generic GPIO
37 binding is used, the amount of cells must be specified as 2. See the below
38 mentioned gpio binding representation for description of particular cells.
40 interrupt-controller: true
49 - $ref: "pinctrl.yaml#"
61 additionalProperties: false
65 additionalProperties: false
67 A pinctrl node should contain at least one subnodes representing the
68 pinctrl groups available on the machine. Each subnode will list the
69 pins it needs, and how they should be configured, with regard to muxer
70 configuration, pullups, drive strength, input enable/disable and input
72 $ref: "/schemas/pinctrl/pincfg-node.yaml"
77 integer array, represents gpio pin number and mux setting.
78 Supported pin number and mux varies for different SoCs, and are
79 defined as macros in <soc>-pinfunc.h directly.
97 input-schmitt-enable: true
99 input-schmitt-disable: true
102 enum: [2, 4, 8, 12, 16]
107 mediatek,pull-up-adv:
109 Pull up setings for 2 pull resistors, R0 and R1. User can
110 configure those special pins. Valid arguments are described as below:
111 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
112 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
113 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
114 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
115 $ref: /schemas/types.yaml#/definitions/uint32
118 mediatek,pull-down-adv:
120 Pull down settings for 2 pull resistors, R0 and R1. User can
121 configure those special pins. Valid arguments are described as below:
122 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
123 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
124 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
125 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
126 $ref: /schemas/types.yaml#/definitions/uint32
131 An integer describing the steps for output level shifter duty
132 cycle when asserted (high pulse width adjustment). Valid arguments
134 $ref: /schemas/types.yaml#/definitions/uint32
138 An integer describing the steps for input level shifter duty cycle
139 when asserted (high pulse width adjustment). Valid arguments are
141 $ref: /schemas/types.yaml#/definitions/uint32
146 additionalProperties: false
150 #include <dt-bindings/interrupt-controller/irq.h>
151 #include <dt-bindings/interrupt-controller/arm-gic.h>
152 #include <dt-bindings/pinctrl/mt6797-pinfunc.h>
155 #address-cells = <2>;
158 pio: pinctrl@10005000 {
159 compatible = "mediatek,mt6797-pinctrl";
160 reg = <0 0x10005000 0 0x1000>,
161 <0 0x10002000 0 0x400>,
162 <0 0x10002400 0 0x400>,
163 <0 0x10002800 0 0x400>,
164 <0 0x10002C00 0 0x400>;
165 reg-names = "gpio", "iocfgl", "iocfgb", "iocfgr", "iocfgt";
169 uart_pins_a: uart-0 {
171 pinmux = <MT6797_GPIO232__FUNC_URXD1>,
172 <MT6797_GPIO233__FUNC_UTXD1>;