1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek MT6779 Pin Controller Device Tree Bindings
10 - Andy Teng <andy.teng@mediatek.com>
13 The pin controller node should be the child of a syscon node with the
15 - compatible: "syscon"
19 const: mediatek,mt6779-pinctrl
42 Number of cells in GPIO specifier. Since the generic GPIO
43 binding is used, the amount of cells must be specified as 2. See the below
44 mentioned gpio binding representation for description of particular cells.
50 GPIO valid number range.
52 interrupt-controller: true
57 Specifies the summary IRQ.
63 - $ref: "pinctrl.yaml#"
72 - interrupt-controller
83 A pinctrl node should contain at least one subnodes representing the
84 pinctrl groups available on the machine. Each subnode will list the
85 pins it needs, and how they should be configured, with regard to muxer
86 configuration, pullups, drive strength, input enable/disable and input schmitt.
87 $ref: "/schemas/pinctrl/pincfg-node.yaml"
92 integer array, represents gpio pin number and mux setting.
93 Supported pin number and mux varies for different SoCs, and are defined
94 as macros in boot/dts/<soc>-pinfunc.h directly.
110 input-schmitt-enable: true
112 input-schmitt-disable: true
114 mediatek,pull-up-adv:
116 Pull up setings for 2 pull resistors, R0 and R1. User can
117 configure those special pins. Valid arguments are described as below:
118 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
119 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
120 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
121 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
122 $ref: /schemas/types.yaml#/definitions/uint32
125 mediatek,pull-down-adv:
127 Pull down settings for 2 pull resistors, R0 and R1. User can
128 configure those special pins. Valid arguments are described as below:
129 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
130 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
131 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
132 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
133 $ref: /schemas/types.yaml#/definitions/uint32
139 additionalProperties: false
141 additionalProperties: false
145 #include <dt-bindings/interrupt-controller/irq.h>
146 #include <dt-bindings/interrupt-controller/arm-gic.h>
147 #include <dt-bindings/pinctrl/mt6779-pinfunc.h>
150 #address-cells = <2>;
153 pio: pinctrl@10005000 {
154 compatible = "mediatek,mt6779-pinctrl";
155 reg = <0 0x10005000 0 0x1000>,
156 <0 0x11c20000 0 0x1000>,
157 <0 0x11d10000 0 0x1000>,
158 <0 0x11e20000 0 0x1000>,
159 <0 0x11e70000 0 0x1000>,
160 <0 0x11ea0000 0 0x1000>,
161 <0 0x11f20000 0 0x1000>,
162 <0 0x11f30000 0 0x1000>,
163 <0 0x1000b000 0 0x1000>;
164 reg-names = "gpio", "iocfg_rm",
165 "iocfg_br", "iocfg_lm",
166 "iocfg_lb", "iocfg_rt",
167 "iocfg_lt", "iocfg_tl",
171 gpio-ranges = <&pio 0 0 210>;
172 interrupt-controller;
173 #interrupt-cells = <2>;
174 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
176 mmc0_pins_default: mmc0-0 {
178 pinmux = <PINMUX_GPIO168__FUNC_MSDC0_DAT0>,
179 <PINMUX_GPIO172__FUNC_MSDC0_DAT1>,
180 <PINMUX_GPIO169__FUNC_MSDC0_DAT2>,
181 <PINMUX_GPIO177__FUNC_MSDC0_DAT3>,
182 <PINMUX_GPIO170__FUNC_MSDC0_DAT4>,
183 <PINMUX_GPIO173__FUNC_MSDC0_DAT5>,
184 <PINMUX_GPIO171__FUNC_MSDC0_DAT6>,
185 <PINMUX_GPIO174__FUNC_MSDC0_DAT7>,
186 <PINMUX_GPIO167__FUNC_MSDC0_CMD>;
188 mediatek,pull-up-adv = <1>;
191 pinmux = <PINMUX_GPIO176__FUNC_MSDC0_CLK>;
192 mediatek,pull-down-adv = <2>;
195 pinmux = <PINMUX_GPIO178__FUNC_MSDC0_RSTB>;
196 mediatek,pull-up-adv = <0>;
202 pinctrl-0 = <&mmc0_pins_default>;
203 pinctrl-names = "default";