1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/pinctrl/allwinner,sun4i-a10-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 Pin Controller Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
17 GPIO consumers must use three arguments, first the number of the
18 bank, then the pin number inside that bank, and finally the GPIO
24 Interrupts consumers must use three arguments, first the number
25 of the bank, then the pin number inside that bank, and finally
30 - allwinner,sun4i-a10-pinctrl
31 - allwinner,sun5i-a10s-pinctrl
32 - allwinner,sun5i-a13-pinctrl
33 - allwinner,sun6i-a31-pinctrl
34 - allwinner,sun6i-a31-r-pinctrl
35 - allwinner,sun6i-a31s-pinctrl
36 - allwinner,sun7i-a20-pinctrl
37 - allwinner,sun8i-a23-pinctrl
38 - allwinner,sun8i-a23-r-pinctrl
39 - allwinner,sun8i-a33-pinctrl
40 - allwinner,sun8i-a83t-pinctrl
41 - allwinner,sun8i-a83t-r-pinctrl
42 - allwinner,sun8i-h3-pinctrl
43 - allwinner,sun8i-h3-r-pinctrl
44 - allwinner,sun8i-r40-pinctrl
45 - allwinner,sun8i-v3-pinctrl
46 - allwinner,sun8i-v3s-pinctrl
47 - allwinner,sun9i-a80-pinctrl
48 - allwinner,sun9i-a80-r-pinctrl
49 - allwinner,sun50i-a64-pinctrl
50 - allwinner,sun50i-a64-r-pinctrl
51 - allwinner,sun50i-a100-pinctrl
52 - allwinner,sun50i-a100-r-pinctrl
53 - allwinner,sun50i-h5-pinctrl
54 - allwinner,sun50i-h6-pinctrl
55 - allwinner,sun50i-h6-r-pinctrl
56 - allwinner,suniv-f1c100s-pinctrl
57 - nextthing,gr8-pinctrl
66 One interrupt per external interrupt bank supported on the
67 controller, sorted by bank number ascending order.
71 - description: Bus Clock
72 - description: High Frequency Oscillator
73 - description: Low Frequency Oscillator
85 interrupt-controller: true
90 Debouncing periods in microseconds, one period per interrupt
91 bank found in the controller
92 $ref: /schemas/types.yaml#/definitions/uint32-array
97 # It's pretty scary, but the basic idea is that:
98 # - One node name can start with either s- or r- for PRCM nodes,
99 # - Then, the name itself can be any repetition of <string>- (to
100 # accomodate with nodes like uart4-rts-cts-pins), where each
101 # string can be either starting with 'p' but in a string longer
102 # than 3, or something that doesn't start with 'p',
103 # - Then, the bank name is optional and will be between pa and pg,
104 # pl or pm. Some pins groups that have several options will have
105 # the pin numbers then,
106 # - Finally, the name will end with either -pin or pins.
108 "^([rs]-)?(([a-z0-9]{3,}|[a-oq-z][a-z0-9]*?)?-)+?(p[a-ilm][0-9]*?-)??pins?$":
119 $ref: /schemas/types.yaml#/definitions/uint32
120 enum: [10, 20, 30, 40]
126 additionalProperties: false
128 "^vcc-p[a-hlm]-supply$":
130 Power supplies for pin banks.
141 - interrupt-controller
144 # FIXME: We should have the pin bank supplies here, but not a lot of
145 # boards are defining it at the moment so it would generate a lot of
152 - allwinner,sun50i-a100-pinctrl
164 - allwinner,sun9i-a80-pinctrl
176 - allwinner,sun6i-a31-pinctrl
177 - allwinner,sun6i-a31s-pinctrl
178 - allwinner,sun50i-h6-pinctrl
190 - allwinner,sun8i-a23-pinctrl
191 - allwinner,sun8i-a83t-pinctrl
192 - allwinner,sun50i-a64-pinctrl
193 - allwinner,sun50i-h5-pinctrl
194 - allwinner,suniv-f1c100s-pinctrl
206 - allwinner,sun6i-a31-r-pinctrl
207 - allwinner,sun8i-a33-pinctrl
208 - allwinner,sun8i-h3-pinctrl
209 - allwinner,sun8i-v3-pinctrl
210 - allwinner,sun8i-v3s-pinctrl
211 - allwinner,sun9i-a80-r-pinctrl
212 - allwinner,sun50i-h6-r-pinctrl
224 - allwinner,sun4i-a10-pinctrl
225 - allwinner,sun5i-a10s-pinctrl
226 - allwinner,sun5i-a13-pinctrl
227 - allwinner,sun7i-a20-pinctrl
228 - allwinner,sun8i-a23-r-pinctrl
229 - allwinner,sun8i-a83t-r-pinctrl
230 - allwinner,sun8i-h3-r-pinctrl
231 - allwinner,sun8i-r40-pinctrl
232 - allwinner,sun50i-a64-r-pinctrl
233 - allwinner,sun50i-a100-r-pinctrl
234 - nextthing,gr8-pinctrl
242 additionalProperties: false
246 #include <dt-bindings/clock/sun5i-ccu.h>
248 pio: pinctrl@1c20800 {
249 compatible = "allwinner,sun5i-a13-pinctrl";
250 reg = <0x01c20800 0x400>;
252 clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
253 clock-names = "apb", "hosc", "losc";
255 interrupt-controller;
256 #interrupt-cells = <3>;
259 uart1_pe_pins: uart1-pe-pins {
260 pins = "PE10", "PE11";
264 uart1_pg_pins: uart1-pg-pins {