1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/phy/xlnx,zynqmp-psgtr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP Gigabit Transceiver PHY
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 This binding describes the Xilinx ZynqMP Gigabit Transceiver (GTR) PHY. The
14 GTR provides four lanes and is used by USB, SATA, PCIE, Display port and
15 Ethernet SGMII controllers.
21 The cells contain the following arguments.
23 - description: The GTR lane
26 - description: The PHY type
33 - description: The PHY instance
35 maximum: 1 # for DP, SATA or USB
36 maximum: 3 # for PCIE or SGMII
37 - description: The reference clock number
43 - xlnx,zynqmp-psgtr-v1.1
50 Clock for each PS_MGTREFCLK[0-3] reference clock input. Unconnected
51 inputs shall not have an entry.
61 - description: SERDES registers block
62 - description: SIOU registers block
69 xlnx,tx-termination-fix:
71 Include this for fixing functional issue with the TX termination
72 resistance in GT, which can be out of spec for the XCZU9EG silicon
85 const: xlnx,zynqmp-psgtr-v1.1
89 xlnx,tx-termination-fix: false
91 additionalProperties: false
96 compatible = "xlnx,zynqmp-psgtr-v1.1";
97 reg = <0xfd400000 0x40000>,
99 reg-names = "serdes", "siou";
100 clocks = <&refclks 3>, <&refclks 2>, <&refclks 0>;
101 clock-names = "ref1", "ref2", "ref3";