1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
5 $id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: TI J721E WIZ (SERDES Wrapper)
11 - Kishon Vijay Abraham I <kishon@ti.com>
24 description: clock-specifier to represent input to the WIZ
51 assigned-clock-parents:
62 GPIO to signal Type-C cable orientation for lane swap.
63 If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
64 achieve the funtionality of an external type-C plug flip mux.
66 typec-dir-debounce-ms:
71 Number of milliseconds to wait before sampling typec-dir-gpio.
72 If not specified, the default debounce of 100ms will be used.
73 Type-C spec states minimum CC pin debounce of 100 ms and maximum
74 of 200 ms. However, some solutions might need more than 200 ms.
80 WIZ node should have subnodes for each of the PLLs present in
85 description: Phandle to clock nodes representing the two inputs to PLL.
93 assigned-clock-parents:
100 - assigned-clock-parents
102 "^cmn-refclk1?-dig-div$":
105 WIZ node should have subnodes for each of the PMA common refclock
106 provided by the SERDES.
110 description: Phandle to the clock node representing the input to the
123 WIZ node should have subnode for refclk_dig to select the reference
124 clock source for the reference clock used in the PHY and PMA digital
130 description: Phandle to two (Torrent) or four (Sierra) clock nodes representing
131 the inputs to refclk_dig
139 assigned-clock-parents:
146 - assigned-clock-parents
148 "^serdes@[0-9a-f]+$":
151 WIZ node should have '1' subnode for the SERDES. It could be either
152 Sierra SERDES or Torrent SERDES. Sierra SERDES should follow the
153 bindings specified in
154 Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
155 Torrent SERDES should follow the bindings specified in
156 Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
169 additionalProperties: false
173 #include <dt-bindings/soc/ti,sci_pm_domain.h>
176 compatible = "ti,j721e-wiz-16g";
177 #address-cells = <1>;
179 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
180 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
181 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
182 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
183 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
186 ranges = <0x5000000 0x5000000 0x10000>;
189 clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
191 assigned-clocks = <&wiz1_pll0_refclk>;
192 assigned-clock-parents = <&k3_clks 293 13>;
196 clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
198 assigned-clocks = <&wiz1_pll1_refclk>;
199 assigned-clock-parents = <&k3_clks 293 0>;
203 clocks = <&wiz1_refclk_dig>;
207 cmn-refclk1-dig-div {
208 clocks = <&wiz1_pll1_refclk>;
213 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>,
214 <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
216 assigned-clocks = <&wiz0_refclk_dig>;
217 assigned-clock-parents = <&k3_clks 292 11>;
221 compatible = "cdns,ti,sierra-phy-t0";
222 reg-names = "serdes";
223 reg = <0x5000000 0x10000>;
224 #address-cells = <1>;
226 resets = <&serdes_wiz0 0>;
227 reset-names = "sierra_reset";
228 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
229 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";