1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
5 $id: http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: CPSW Port's Interface Mode Selection PHY
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 TI am335x/am437x/dra7(am5)/dm814x CPSW3G Ethernet Subsystem supports
15 two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces.
16 The interface mode is selected by configuring the MII mode selection register(s)
17 (GMII_SEL) in the System Control Module chapter (SCM). GMII_SEL register(s) and
18 bit fields placement in SCM are different between SoCs while fields meaning
21 +-------------------------------+ |SCM |
22 | CPSW | | +---------+ |
23 | +--------------------------------+gmii_sel | |
25 | +----v---+ +--------+ | +--------------+
26 | |Port 1..<--+-->GMII/MII<------->
28 | +--------+ | +--------+ |
39 +-------------------------------+
41 CPSW Port's Interface Mode Selection PHY describes MII interface mode between
42 CPSW Port and Ethernet PHY which depends on Eth PHY and board configuration.
44 CPSW Port's Interface Mode Selection PHY device should defined as child device
45 of SCM node (scm_conf) and can be attached to each CPSW port node using standard
51 - ti,am3352-phy-gmii-sel
52 - ti,dra7xx-phy-gmii-sel
53 - ti,am43xx-phy-gmii-sel
54 - ti,dm814-phy-gmii-sel
55 - ti,am654-phy-gmii-sel
56 - ti,j7200-cpsw5g-phy-gmii-sel
57 - ti,j721e-cpsw9g-phy-gmii-sel
58 - ti,j784s4-cpsw9g-phy-gmii-sel
66 $ref: /schemas/types.yaml#/definitions/uint32-array
68 Required only for QSGMII mode. Array to select the port/s for QSGMII
69 main mode. The size of the array corresponds to the number of QSGMII
70 interfaces and thus, the number of distinct QSGMII main ports,
71 supported by the device. If the device supports two QSGMII interfaces
72 but only one QSGMII interface is desired, repeat the QSGMII main port
73 value corresponding to the QSGMII interface in the array.
86 - ti,dra7xx-phy-gmii-sel
87 - ti,dm814-phy-gmii-sel
88 - ti,am654-phy-gmii-sel
89 - ti,j7200-cpsw5g-phy-gmii-sel
90 - ti,j721e-cpsw9g-phy-gmii-sel
91 - ti,j784s4-cpsw9g-phy-gmii-sel
96 description: CPSW port number (starting from 1)
103 - ti,j7200-cpsw5g-phy-gmii-sel
106 ti,qsgmii-main-ports:
117 - ti,j721e-cpsw9g-phy-gmii-sel
118 - ti,j784s4-cpsw9g-phy-gmii-sel
121 ti,qsgmii-main-ports:
134 - ti,j7200-cpsw5g-phy-gmii-sel
135 - ti,j721e-cpsw9g-phy-gmii-sel
136 - ti,j784s4-cpsw9g-phy-gmii-sel
139 ti,qsgmii-main-ports: false
146 - ti,am3352-phy-gmii-sel
147 - ti,am43xx-phy-gmii-sel
153 - CPSW port number (starting from 1)
161 additionalProperties: false
165 phy_gmii_sel: phy@650 {
166 compatible = "ti,am3352-phy-gmii-sel";