1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 High-Speed (HS) PHY
10 This describes the devicetree bindings for PHY interfaces built into
11 USB3 controller implemented on Socionext UniPhier SoCs.
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about High-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro5-usb3-hsphy
22 - socionext,uniphier-pxs2-usb3-hsphy
23 - socionext,uniphier-ld20-usb3-hsphy
24 - socionext,uniphier-pxs3-usb3-hsphy
25 - socionext,uniphier-nx1-usb3-hsphy
45 description: A phandle to the regulator for USB VBUS
50 Phandles to nvmem cell that contains the trimming data.
51 Available only for HS-PHY implemented on LD20 and PXs3, and
52 if unspecified, default value is used.
60 Should be the following names, which correspond to each nvmem-cells.
61 All of the 3 parameters associated with the above names are
62 required for each port, if any one is omitted, the trimming data
63 of the port will not be set at all.
70 const: socionext,uniphier-pro5-usb3-hsphy
92 - socionext,uniphier-pxs2-usb3-hsphy
93 - socionext,uniphier-ld20-usb3-hsphy
115 - socionext,uniphier-pxs3-usb3-hsphy
116 - socionext,uniphier-nx1-usb3-hsphy
145 additionalProperties: false
149 usb_hsphy0: phy@200 {
150 compatible = "socionext,uniphier-ld20-usb3-hsphy";
153 clock-names = "link", "phy";
154 clocks = <&sys_clk 14>, <&sys_clk 16>;
155 reset-names = "link", "phy";
156 resets = <&sys_rst 14>, <&sys_rst 16>;
157 vbus-supply = <&usb_vbus0>;
158 nvmem-cell-names = "rterm", "sel_t", "hs_i";
159 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, <&usb_hs_i0>;