1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier PCIe PHY
10 This describes the devicetree bindings for PHY interface built into
11 PCIe controller implemented on Socionext UniPhier SoCs.
14 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19 - socionext,uniphier-pro5-pcie-phy
20 - socionext,uniphier-ld20-pcie-phy
21 - socionext,uniphier-pxs3-pcie-phy
24 description: PHY register region (offset and length)
38 - const: link # for others
49 - const: link # for others
52 $ref: /schemas/types.yaml#/definitions/phandle
53 description: A phandle to system control to set configurations for phy
64 additionalProperties: false
68 pcie_phy: phy@66038000 {
69 compatible = "socionext,uniphier-ld20-pcie-phy";
70 reg = <0x66038000 0x4000>;
73 clocks = <&sys_clk 24>;
75 resets = <&sys_rst 24>;
76 socionext,syscon = <&soc_glue>;