1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/phy/samsung,usb2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S5P/Exynos SoC USB 2.0 PHY
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Marek Szyprowski <m.szyprowski@samsung.com>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
15 The first phandle argument in the PHY specifier identifies the PHY, its
16 meaning is compatible dependent. For the currently supported SoCs (Exynos4210
17 and Exynos4212) it is as follows::
18 0 - USB device ("device"),
19 1 - USB host ("host"),
22 Exynos3250 has only USB device phy available as phy 0.
24 Exynos4210 and Exynos4212 use mode switching and require that mode switch
30 - samsung,exynos3250-usb2-phy
31 - samsung,exynos4210-usb2-phy
32 - samsung,exynos4x12-usb2-phy
33 - samsung,exynos5250-usb2-phy
34 - samsung,exynos5420-usb2-phy
35 - samsung,s5pv210-usb2-phy
39 - description: PHY module gate clock.
40 - description: Reference rate clock of PHY module.
53 samsung,pmureg-phandle:
54 $ref: /schemas/types.yaml#/definitions/phandle
56 Phandle to PMU system controller interface.
58 samsung,sysreg-phandle:
59 $ref: /schemas/types.yaml#/definitions/phandle
61 Phandle to system registers interface.
73 - samsung,pmureg-phandle
81 - samsung,exynos4x12-usb2-phy
82 - samsung,exynos5250-usb2-phy
83 - samsung,exynos5420-usb2-phy
86 - samsung,sysreg-phandle
88 additionalProperties: false
92 #include <dt-bindings/clock/exynos5420.h>
95 compatible = "samsung,exynos5420-usb2-phy";
96 reg = <0x12130000 0x100>;
98 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
99 clock-names = "phy", "ref";
100 samsung,sysreg-phandle = <&sysreg_system_controller>;
101 samsung,pmureg-phandle = <&pmu_system_controller>;