1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip PCIe v3 phy
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3568-pcie3-phy
16 - rockchip,rk3588-pcie3-phy
30 description: which lanes (by position) should be mapped to which
31 controller (value). 0 means lane disabled, higher value means used.
32 (controller-number +1 )
33 $ref: /schemas/types.yaml#/definitions/uint32-array
50 $ref: /schemas/types.yaml#/definitions/phandle
51 description: phandle to the syscon managing the phy "general register files"
54 $ref: /schemas/types.yaml#/definitions/phandle
55 description: phandle to the syscon managing the pipe "general register files"
68 - rockchip,rk3588-pcie3-phy
87 additionalProperties: false
91 #include <dt-bindings/clock/rk3568-cru.h>
92 pcie30phy: phy@fe8c0000 {
93 compatible = "rockchip,rk3568-pcie3-phy";
94 reg = <0xfe8c0000 0x20000>;
96 clocks = <&pmucru CLK_PCIE30PHY_REF_M>,
97 <&pmucru CLK_PCIE30PHY_REF_N>,
98 <&cru PCLK_PCIE30PHY>;
99 clock-names = "refclk_m", "refclk_n", "pclk";
100 resets = <&cru SRST_PCIE30PHY>;
102 rockchip,phy-grf = <&pcie30_phy_grf>;