1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: "http://devicetree.org/schemas/phy/qcom,usb-hs-28nm.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Qualcomm Synopsys DesignWare Core 28nm High-Speed PHY
10 - Bryan O'Donoghue <bryan.odonoghue@linaro.org>
13 Qualcomm Low-Speed, Full-Speed, Hi-Speed 28nm USB PHY
18 - qcom,usb-hs-28nm-femtophy
19 - qcom,usb-hs-28nm-mdm9607
29 - description: rpmcc ref clock
30 - description: PHY AHB clock
31 - description: Rentention clock
41 - description: PHY core reset
42 - description: POR reset
50 description: phandle to the regulator VDD supply node.
53 description: phandle to the regulator 1.8V supply node.
56 description: phandle to the regulator 3.3V supply node.
70 additionalProperties: false
74 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
75 #include <dt-bindings/clock/qcom,rpmcc.h>
76 usb2_phy_prim: phy@7a000 {
77 compatible = "qcom,usb-hs-28nm-femtophy";
78 reg = <0x0007a000 0x200>;
80 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
81 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
82 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
83 clock-names = "ref", "ahb", "sleep";
84 resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>,
85 <&gcc GCC_USB2A_PHY_BCR>;
86 reset-names = "phy", "por";
87 vdd-supply = <&vreg_l4_1p2>;
88 vdda1p8-supply = <&vreg_l5_1p8>;
89 vdda3p3-supply = <&vreg_l12_3p3>;