1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: "http://devicetree.org/schemas/phy/qcom,usb-hs-28nm.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Qualcomm Synopsys DesignWare Core 28nm High-Speed PHY
10 - Bryan O'Donoghue <bryan.odonoghue@linaro.org>
13 Qualcomm Low-Speed, Full-Speed, Hi-Speed 28nm USB PHY
18 - qcom,usb-hs-28nm-femtophy
28 - description: rpmcc ref clock
29 - description: PHY AHB clock
30 - description: Rentention clock
40 - description: PHY core reset
41 - description: POR reset
49 description: phandle to the regulator VDD supply node.
52 description: phandle to the regulator 1.8V supply node.
55 description: phandle to the regulator 3.3V supply node.
69 additionalProperties: false
73 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
74 #include <dt-bindings/clock/qcom,rpmcc.h>
75 usb2_phy_prim: phy@7a000 {
76 compatible = "qcom,usb-hs-28nm-femtophy";
77 reg = <0x0007a000 0x200>;
79 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
80 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
81 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
82 clock-names = "ref", "ahb", "sleep";
83 resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>,
84 <&gcc GCC_USB2A_PHY_BCR>;
85 reset-names = "phy", "por";
86 vdd-supply = <&vreg_l4_1p2>;
87 vdda1p8-supply = <&vreg_l5_1p8>;
88 vdda3p3-supply = <&vreg_l12_3p3>;