1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
5 $id: "http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm QUSB2 phy controller
11 - Manu Gautam <mgautam@codeaurora.org>
14 QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
21 - qcom,ipq8074-qusb2-phy
22 - qcom,msm8996-qusb2-phy
23 - qcom,msm8998-qusb2-phy
26 - qcom,sc7180-qusb2-phy
27 - qcom,sdm845-qusb2-phy
28 - const: qcom,qusb2-v2-phy
39 - description: phy config clock
40 - description: 19.2 MHz ref clk
41 - description: phy interface clock (Optional)
53 Phandle to 1.8V regulator supply to PHY refclk pll block.
57 Phandle to 3.1V regulator supply to Dp/Dm port signals.
62 Phandle to reset to phy block.
67 Phandle to nvmem cell that contains 'HS Tx trim'
68 tuning parameter value for qusb2 phy.
72 Phandle to TCSR syscon register region.
73 $ref: /schemas/types.yaml#/definitions/phandle
79 const: qcom,qusb2-v2-phy
82 qcom,imp-res-offset-value:
84 It is a 6 bit value that specifies offset to be
85 added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
86 tuning parameter that may vary for different boards of same SOC.
87 $ref: /schemas/types.yaml#/definitions/uint32
94 It is a 6 bit value that specifies bias-ctrl-value. It is a PHY
95 tuning parameter that may vary for different boards of same SOC.
96 $ref: /schemas/types.yaml#/definitions/uint32
101 qcom,charge-ctrl-value:
103 It is a 2 bit value that specifies charge-ctrl-value. It is a PHY
104 tuning parameter that may vary for different boards of same SOC.
105 $ref: /schemas/types.yaml#/definitions/uint32
110 qcom,hstx-trim-value:
112 It is a 4 bit value that specifies tuning for HSTX
114 Possible range is - 15mA to 24mA (stepsize of 600 uA).
115 See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
116 $ref: /schemas/types.yaml#/definitions/uint32
121 qcom,preemphasis-level:
123 It is a 2 bit value that specifies pre-emphasis level.
124 Possible range is 0 to 15% (stepsize of 5%).
125 See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
126 $ref: /schemas/types.yaml#/definitions/uint32
131 qcom,preemphasis-width:
133 It is a 1 bit value that specifies how long the HSTX
134 pre-emphasis (specified using qcom,preemphasis-level) must be in
135 effect. Duration could be half-bit of full-bit.
136 See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
137 $ref: /schemas/types.yaml#/definitions/uint32
142 qcom,hsdisc-trim-value:
144 It is a 2 bit value tuning parameter that control disconnect
145 threshold and may vary for different boards of same SOC.
146 $ref: /schemas/types.yaml#/definitions/uint32
158 - vdda-phy-dpdm-supply
161 additionalProperties: false
165 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
166 hsusb_phy: phy@7411000 {
167 compatible = "qcom,msm8996-qusb2-phy";
168 reg = <0x7411000 0x180>;
171 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
172 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
173 clock-names = "cfg_ahb", "ref";
175 vdda-pll-supply = <&pm8994_l12>;
176 vdda-phy-dpdm-supply = <&pm8994_l24>;
178 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
179 nvmem-cells = <&qusb2p_hstx_trim>;