1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
5 $id: "http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm QUSB2 phy controller
11 - Manu Gautam <mgautam@codeaurora.org>
14 QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
21 - qcom,ipq8074-qusb2-phy
22 - qcom,msm8996-qusb2-phy
23 - qcom,msm8998-qusb2-phy
24 - qcom,sdm660-qusb2-phy
25 - qcom,ipq6018-qusb2-phy
26 - qcom,sm4250-qusb2-phy
27 - qcom,sm6115-qusb2-phy
30 - qcom,sc7180-qusb2-phy
31 - qcom,sdm845-qusb2-phy
32 - const: qcom,qusb2-v2-phy
42 - description: phy config clock
43 - description: 19.2 MHz ref clk
44 - description: phy interface clock (Optional)
55 Phandle to 1.8V regulator supply to PHY refclk pll block.
59 Phandle to 3.1V regulator supply to Dp/Dm port signals.
64 Phandle to reset to phy block.
69 Phandle to nvmem cell that contains 'HS Tx trim'
70 tuning parameter value for qusb2 phy.
74 Phandle to TCSR syscon register region.
75 $ref: /schemas/types.yaml#/definitions/phandle
81 const: qcom,qusb2-v2-phy
84 qcom,imp-res-offset-value:
86 It is a 6 bit value that specifies offset to be
87 added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
88 tuning parameter that may vary for different boards of same SOC.
89 $ref: /schemas/types.yaml#/definitions/uint32
96 It is a 6 bit value that specifies bias-ctrl-value. It is a PHY
97 tuning parameter that may vary for different boards of same SOC.
98 $ref: /schemas/types.yaml#/definitions/uint32
103 qcom,charge-ctrl-value:
105 It is a 2 bit value that specifies charge-ctrl-value. It is a PHY
106 tuning parameter that may vary for different boards of same SOC.
107 $ref: /schemas/types.yaml#/definitions/uint32
112 qcom,hstx-trim-value:
114 It is a 4 bit value that specifies tuning for HSTX
116 Possible range is - 15mA to 24mA (stepsize of 600 uA).
117 See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
118 $ref: /schemas/types.yaml#/definitions/uint32
123 qcom,preemphasis-level:
125 It is a 2 bit value that specifies pre-emphasis level.
126 Possible range is 0 to 15% (stepsize of 5%).
127 See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
128 $ref: /schemas/types.yaml#/definitions/uint32
133 qcom,preemphasis-width:
135 It is a 1 bit value that specifies how long the HSTX
136 pre-emphasis (specified using qcom,preemphasis-level) must be in
137 effect. Duration could be half-bit of full-bit.
138 See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
139 $ref: /schemas/types.yaml#/definitions/uint32
144 qcom,hsdisc-trim-value:
146 It is a 2 bit value tuning parameter that control disconnect
147 threshold and may vary for different boards of same SOC.
148 $ref: /schemas/types.yaml#/definitions/uint32
160 - vdda-phy-dpdm-supply
163 additionalProperties: false
167 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
168 hsusb_phy: phy@7411000 {
169 compatible = "qcom,msm8996-qusb2-phy";
170 reg = <0x7411000 0x180>;
173 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
174 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
175 clock-names = "cfg_ahb", "ref";
177 vdda-pll-supply = <&pm8994_l12>;
178 vdda-phy-dpdm-supply = <&pm8994_l24>;
180 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
181 nvmem-cells = <&qusb2p_hstx_trim>;