1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-usb3-dp-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm QMP USB3 DP PHY controller
11 - Manu Gautam <mgautam@codeaurora.org>
16 - qcom,sc7180-qmp-usb3-dp-phy
17 - qcom,sdm845-qmp-usb3-dp-phy
18 - qcom,sm8250-qmp-usb3-dp-phy
21 - description: Address and length of PHY's USB serdes block.
22 - description: Address and length of the DP_COM control block.
23 - description: Address and length of PHY's DP serdes block.
44 - description: Phy aux clock.
45 - description: Phy config clock.
46 - description: 19.2 MHz ref clk.
47 - description: Phy common block aux clock.
58 - description: reset of phy block.
59 - description: phy common block reset.
68 Phandle to a regulator supply to PHY core block.
72 Phandle to 1.8V regulator supply to PHY refclk pll block.
76 Phandle to a regulator supply to any specific refclk pll block.
80 "^usb3-phy@[0-9a-f]+$":
88 - description: Address and length of TX.
89 - description: Address and length of RX.
90 - description: Address and length of PCS.
91 - description: Address and length of TX2.
92 - description: Address and length of RX2.
93 - description: Address and length of pcs_misc.
97 - description: pipe clock
105 - const: usb3_phy_pipe_clk_src
120 "^dp-phy@[0-9a-f]+$":
128 - description: Address and length of TX.
129 - description: Address and length of RX.
130 - description: Address and length of PCS.
131 - description: Address and length of TX2.
132 - description: Address and length of RX2.
159 additionalProperties: false
163 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
164 usb_1_qmpphy: phy-wrapper@88e9000 {
165 compatible = "qcom,sdm845-qmp-usb3-dp-phy";
166 reg = <0x088e9000 0x18c>,
169 reg-names = "usb", "dp_com", "dp";
171 #address-cells = <1>;
173 ranges = <0x0 0x088e9000 0x2000>;
175 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
176 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
177 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
178 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
179 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
181 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
182 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
183 reset-names = "phy", "common";
185 vdda-phy-supply = <&vdda_usb2_ss_1p2>;
186 vdda-pll-supply = <&vdda_usb2_ss_core>;
197 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
198 clock-names = "pipe0";
199 clock-output-names = "usb3_phy_pipe_clk_src";
203 reg = <0xa200 0x200>,