Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2
   3 %YAML 1.2
   4 ---
   5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-usb3-dp-phy.yaml#"
   6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
   7
   8 title: Qualcomm QMP USB3 DP PHY controller
   9
  10 maintainers:
  11   - Manu Gautam <mgautam@codeaurora.org>
  12
  13 properties:
  14   compatible:
  15     const:
  16       qcom,sdm845-qmp-usb3-phy
  17   reg:
  18     items:
  19       - description: Address and length of PHY's common serdes block.
  20       - description: Address and length of the DP_COM control block.
  21
  22   reg-names:
  23     items:
  24       - const: reg-base
  25       - const: dp_com
  26
  27   "#clock-cells":
  28      enum: [ 1, 2 ]
  29
  30   "#address-cells":
  31     enum: [ 1, 2 ]
  32
  33   "#size-cells":
  34     enum: [ 1, 2 ]
  35
  36   clocks:
  37     items:
  38       - description: Phy aux clock.
  39       - description: Phy config clock.
  40       - description: 19.2 MHz ref clk.
  41       - description: Phy common block aux clock.
  42
  43   clock-names:
  44     items:
  45       - const: aux
  46       - const: cfg_ahb
  47       - const: ref
  48       - const: com_aux
  49
  50   resets:
  51     items:
  52       - description: reset of phy block.
  53       - description: phy common block reset.
  54
  55   reset-names:
  56     items:
  57       - const: phy
  58       - const: common
  59
  60   vdda-phy-supply:
  61     description:
  62         Phandle to a regulator supply to PHY core block.
  63
  64   vdda-pll-supply:
  65     description:
  66         Phandle to 1.8V regulator supply to PHY refclk pll block.
  67
  68   vddp-ref-clk-supply:
  69     description:
  70         Phandle to a regulator supply to any specific refclk
  71         pll block.
  72
  73 #Required nodes:
  74 patternProperties:
  75   "^phy@[0-9a-f]+$":
  76     type: object
  77     description:
  78       Each device node of QMP phy is required to have as many child nodes as
  79       the number of lanes the PHY has.
  80
  81 required:
  82   - compatible
  83   - reg
  84   - reg-names
  85   - "#clock-cells"
  86   - "#address-cells"
  87   - "#size-cells"
  88   - clocks
  89   - clock-names
  90   - resets
  91   - reset-names
  92   - vdda-phy-supply
  93   - vdda-pll-supply
  94
  95 additionalProperties: false
  96
  97 examples:
  98   - |
  99     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
 100     usb_1_qmpphy: phy-wrapper@88e9000 {
 101         compatible = "qcom,sdm845-qmp-usb3-phy";
 102         reg = <0 0x088e9000 0 0x18c>,
 103               <0 0x088e8000 0 0x10>;
 104         reg-names = "reg-base", "dp_com";
 105         #clock-cells = <1>;
 106         #address-cells = <2>;
 107         #size-cells = <2>;
 108
 109         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
 110                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
 111                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
 112                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
 113         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
 114
 115         resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
 116                  <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
 117         reset-names = "phy", "common";
 118
 119         vdda-phy-supply = <&vdda_usb2_ss_1p2>;
 120         vdda-pll-supply = <&vdda_usb2_ss_core>;
 121
 122         usb_1_ssphy: phy@88e9200 {
 123                 reg = <0 0x088e9200 0 0x128>,
 124                       <0 0x088e9400 0 0x200>,
 125                       <0 0x088e9c00 0 0x218>,
 126                       <0 0x088e9600 0 0x128>,
 127                       <0 0x088e9800 0 0x200>,
 128                       <0 0x088e9a00 0 0x100>;
 129                 #clock-cells = <0>;
 130                 #phy-cells = <0>;
 131                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
 132                 clock-names = "pipe0";
 133                 clock-output-names = "usb3_phy_pipe_clk_src";
 134             };
 135         };