1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm QMP PHY controller
11 - Manu Gautam <mgautam@codeaurora.org>
14 QMP phy controller supports physical layer functionality for a number of
15 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
20 - qcom,ipq6018-qmp-pcie-phy
21 - qcom,ipq8074-qmp-pcie-phy
22 - qcom,ipq8074-qmp-usb3-phy
23 - qcom,msm8996-qmp-pcie-phy
24 - qcom,msm8996-qmp-ufs-phy
25 - qcom,msm8996-qmp-usb3-phy
26 - qcom,msm8998-qmp-pcie-phy
27 - qcom,msm8998-qmp-ufs-phy
28 - qcom,msm8998-qmp-usb3-phy
29 - qcom,sc7180-qmp-usb3-phy
30 - qcom,sc8180x-qmp-ufs-phy
31 - qcom,sc8180x-qmp-usb3-phy
32 - qcom,sdm845-qhp-pcie-phy
33 - qcom,sdm845-qmp-pcie-phy
34 - qcom,sdm845-qmp-ufs-phy
35 - qcom,sdm845-qmp-usb3-phy
36 - qcom,sdm845-qmp-usb3-uni-phy
37 - qcom,sm8150-qmp-ufs-phy
38 - qcom,sm8150-qmp-usb3-phy
39 - qcom,sm8150-qmp-usb3-uni-phy
40 - qcom,sm8250-qmp-ufs-phy
41 - qcom,sm8250-qmp-gen3x1-pcie-phy
42 - qcom,sm8250-qmp-gen3x2-pcie-phy
43 - qcom,sm8250-qmp-modem-pcie-phy
44 - qcom,sm8250-qmp-usb3-phy
45 - qcom,sm8250-qmp-usb3-uni-phy
46 - qcom,sm8350-qmp-ufs-phy
47 - qcom,sm8350-qmp-usb3-phy
48 - qcom,sm8350-qmp-usb3-uni-phy
49 - qcom,sdx55-qmp-pcie-phy
50 - qcom,sdx55-qmp-usb3-uni-phy
55 - description: Address and length of PHY's common serdes block.
56 - description: Address and length of PHY's DP_COM control block.
87 Phandle to a regulator supply to PHY core block.
91 Phandle to 1.8V regulator supply to PHY refclk pll block.
95 Phandle to a regulator supply to any specific refclk pll block.
102 Each device node of QMP phy is required to have as many child nodes as
103 the number of lanes the PHY has.
119 additionalProperties: false
127 - qcom,sdm845-qmp-usb3-uni-phy
132 - description: Phy aux clock.
133 - description: Phy config clock.
134 - description: 19.2 MHz ref clk.
135 - description: Phy common block aux clock.
144 - description: reset of phy block.
145 - description: phy common block reset.
155 - qcom,sdx55-qmp-usb3-uni-phy
160 - description: Phy aux clock.
161 - description: Phy config clock.
162 - description: 19.2 MHz ref clk.
170 - description: reset of phy block.
171 - description: phy common block reset.
181 - qcom,msm8996-qmp-pcie-phy
186 - description: Phy aux clock.
187 - description: Phy config clock.
188 - description: 19.2 MHz ref clk.
196 - description: reset of phy block.
197 - description: phy common block reset.
198 - description: phy's ahb cfg block reset.
209 - qcom,ipq8074-qmp-usb3-phy
210 - qcom,msm8996-qmp-usb3-phy
211 - qcom,msm8998-qmp-pcie-phy
212 - qcom,msm8998-qmp-usb3-phy
217 - description: Phy aux clock.
218 - description: Phy config clock.
219 - description: 19.2 MHz ref clk.
227 - description: reset of phy block.
228 - description: phy common block reset.
238 - qcom,msm8996-qmp-ufs-phy
243 - description: 19.2 MHz ref clk.
249 - description: PHY reset in the UFS controller.
258 - qcom,msm8998-qmp-ufs-phy
259 - qcom,sdm845-qmp-ufs-phy
260 - qcom,sm8150-qmp-ufs-phy
261 - qcom,sm8250-qmp-ufs-phy
266 - description: 19.2 MHz ref clk.
267 - description: Phy reference aux clock.
274 - description: PHY reset in the UFS controller.
283 - qcom,ipq8074-qmp-pcie-phy
288 - description: pipe clk.
294 - description: reset of phy block.
295 - description: phy common block reset.
305 - qcom,ipq6018-qmp-pcie-phy
310 - description: Phy aux clock.
311 - description: Phy config clock.
318 - description: reset of phy block.
319 - description: phy common block reset.
329 - qcom,sdm845-qhp-pcie-phy
330 - qcom,sdm845-qmp-pcie-phy
331 - qcom,sdx55-qmp-pcie-phy
332 - qcom,sm8250-qmp-gen3x1-pcie-phy
333 - qcom,sm8250-qmp-gen3x2-pcie-phy
334 - qcom,sm8250-qmp-modem-pcie-phy
339 - description: Phy aux clock.
340 - description: Phy config clock.
341 - description: 19.2 MHz ref clk.
342 - description: Phy refgen clk.
351 - description: reset of phy block.
360 - qcom,sm8150-qmp-usb3-phy
361 - qcom,sm8150-qmp-usb3-uni-phy
362 - qcom,sm8250-qmp-usb3-uni-phy
363 - qcom,sm8350-qmp-usb3-uni-phy
368 - description: Phy aux clock.
369 - description: 19.2 MHz ref clk source.
370 - description: 19.2 MHz ref clk.
371 - description: Phy common block aux clock.
380 - description: reset of phy block.
381 - description: phy common block reset.
391 - qcom,sm8250-qmp-usb3-phy
392 - qcom,sm8350-qmp-usb3-phy
397 - description: Phy aux clock.
398 - description: 19.2 MHz ref clk.
399 - description: Phy common block aux clock.
407 - description: reset of phy block.
408 - description: phy common block reset.
416 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
417 usb_2_qmpphy: phy-wrapper@88eb000 {
418 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
419 reg = <0x088eb000 0x18c>;
421 #address-cells = <1>;
423 ranges = <0x0 0x088eb000 0x2000>;
425 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK >,
426 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
427 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
428 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
429 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
431 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
432 <&gcc GCC_USB3_PHY_SEC_BCR>;
433 reset-names = "phy", "common";
435 vdda-phy-supply = <&vdda_usb2_ss_1p2>;
436 vdda-pll-supply = <&vdda_usb2_ss_core>;
438 usb_2_ssphy: phy@200 {
445 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
446 clock-names = "pipe0";
447 clock-output-names = "usb3_uni_phy_pipe_clk_src";