1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm QMP PHY controller
11 - Manu Gautam <mgautam@codeaurora.org>
14 QMP phy controller supports physical layer functionality for a number of
15 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
20 - qcom,ipq8074-qmp-pcie-phy
21 - qcom,ipq8074-qmp-usb3-phy
22 - qcom,msm8996-qmp-pcie-phy
23 - qcom,msm8996-qmp-ufs-phy
24 - qcom,msm8996-qmp-usb3-phy
25 - qcom,msm8998-qmp-pcie-phy
26 - qcom,msm8998-qmp-ufs-phy
27 - qcom,msm8998-qmp-usb3-phy
28 - qcom,sdm845-qhp-pcie-phy
29 - qcom,sdm845-qmp-pcie-phy
30 - qcom,sdm845-qmp-ufs-phy
31 - qcom,sdm845-qmp-usb3-uni-phy
32 - qcom,sm8150-qmp-ufs-phy
33 - qcom,sm8250-qmp-ufs-phy
34 - qcom,sm8250-qmp-gen3x1-pcie-phy
35 - qcom,sm8250-qmp-gen3x2-pcie-phy
36 - qcom,sm8250-qmp-modem-pcie-phy
40 - description: Address and length of PHY's common serdes block.
71 Phandle to a regulator supply to PHY core block.
75 Phandle to 1.8V regulator supply to PHY refclk pll block.
79 Phandle to a regulator supply to any specific refclk pll block.
86 Each device node of QMP phy is required to have as many child nodes as
87 the number of lanes the PHY has.
103 additionalProperties: false
111 - qcom,sdm845-qmp-usb3-uni-phy
116 - description: Phy aux clock.
117 - description: Phy config clock.
118 - description: 19.2 MHz ref clk.
119 - description: Phy common block aux clock.
128 - description: reset of phy block.
129 - description: phy common block reset.
139 - qcom,msm8996-qmp-pcie-phy
144 - description: Phy aux clock.
145 - description: Phy config clock.
146 - description: 19.2 MHz ref clk.
154 - description: reset of phy block.
155 - description: phy common block reset.
156 - description: phy's ahb cfg block reset.
167 - qcom,ipq8074-qmp-usb3-phy
168 - qcom,msm8996-qmp-usb3-phy
169 - qcom,msm8998-qmp-pcie-phy
170 - qcom,msm8998-qmp-usb3-phy
175 - description: Phy aux clock.
176 - description: Phy config clock.
177 - description: 19.2 MHz ref clk.
185 - description: reset of phy block.
186 - description: phy common block reset.
196 - qcom,msm8996-qmp-ufs-phy
201 - description: 19.2 MHz ref clk.
207 - description: PHY reset in the UFS controller.
216 - qcom,msm8998-qmp-ufs-phy
217 - qcom,sdm845-qmp-ufs-phy
218 - qcom,sm8150-qmp-ufs-phy
219 - qcom,sm8250-qmp-ufs-phy
224 - description: 19.2 MHz ref clk.
225 - description: Phy reference aux clock.
232 - description: PHY reset in the UFS controller.
241 - qcom,ipq8074-qmp-pcie-phy
246 - description: pipe clk.
252 - description: reset of phy block.
253 - description: phy common block reset.
263 - qcom,sdm845-qhp-pcie-phy
264 - qcom,sdm845-qmp-pcie-phy
265 - qcom,sm8250-qmp-gen3x1-pcie-phy
266 - qcom,sm8250-qmp-gen3x2-pcie-phy
267 - qcom,sm8250-qmp-modem-pcie-phy
272 - description: Phy aux clock.
273 - description: Phy config clock.
274 - description: 19.2 MHz ref clk.
275 - description: Phy refgen clk.
284 - description: reset of phy block.
291 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
292 usb_2_qmpphy: phy-wrapper@88eb000 {
293 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
294 reg = <0x088eb000 0x18c>;
296 #address-cells = <1>;
298 ranges = <0x0 0x088eb000 0x2000>;
300 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK >,
301 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
302 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
303 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
304 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
306 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
307 <&gcc GCC_USB3_PHY_SEC_BCR>;
308 reset-names = "phy", "common";
310 vdda-phy-supply = <&vdda_usb2_ss_1p2>;
311 vdda-pll-supply = <&vdda_usb2_ss_core>;
313 usb_2_ssphy: phy@200 {
320 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
321 clock-names = "pipe0";
322 clock-output-names = "usb3_uni_phy_pipe_clk_src";