1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm QMP PHY controller
11 - Manu Gautam <mgautam@codeaurora.org>
14 QMP phy controller supports physical layer functionality for a number of
15 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
20 - qcom,ipq6018-qmp-pcie-phy
21 - qcom,ipq6018-qmp-usb3-phy
22 - qcom,ipq8074-qmp-pcie-phy
23 - qcom,ipq8074-qmp-usb3-phy
24 - qcom,msm8996-qmp-pcie-phy
25 - qcom,msm8996-qmp-ufs-phy
26 - qcom,msm8996-qmp-usb3-phy
27 - qcom,msm8998-qmp-pcie-phy
28 - qcom,msm8998-qmp-ufs-phy
29 - qcom,msm8998-qmp-usb3-phy
30 - qcom,sc7180-qmp-usb3-phy
31 - qcom,sc8180x-qmp-pcie-phy
32 - qcom,sc8180x-qmp-ufs-phy
33 - qcom,sc8180x-qmp-usb3-phy
34 - qcom,sdm845-qhp-pcie-phy
35 - qcom,sdm845-qmp-pcie-phy
36 - qcom,sdm845-qmp-ufs-phy
37 - qcom,sdm845-qmp-usb3-phy
38 - qcom,sdm845-qmp-usb3-uni-phy
39 - qcom,sm6115-qmp-ufs-phy
40 - qcom,sm8150-qmp-ufs-phy
41 - qcom,sm8150-qmp-usb3-phy
42 - qcom,sm8150-qmp-usb3-uni-phy
43 - qcom,sm8250-qmp-ufs-phy
44 - qcom,sm8250-qmp-gen3x1-pcie-phy
45 - qcom,sm8250-qmp-gen3x2-pcie-phy
46 - qcom,sm8250-qmp-modem-pcie-phy
47 - qcom,sm8250-qmp-usb3-phy
48 - qcom,sm8250-qmp-usb3-uni-phy
49 - qcom,sm8350-qmp-ufs-phy
50 - qcom,sm8350-qmp-usb3-phy
51 - qcom,sm8350-qmp-usb3-uni-phy
52 - qcom,sdx55-qmp-pcie-phy
53 - qcom,sdx55-qmp-usb3-uni-phy
58 - description: Address and length of PHY's common serdes block.
59 - description: Address and length of PHY's DP_COM control block.
90 Phandle to a regulator supply to PHY core block.
94 Phandle to 1.8V regulator supply to PHY refclk pll block.
98 Phandle to a regulator supply to any specific refclk pll block.
105 Each device node of QMP phy is required to have as many child nodes as
106 the number of lanes the PHY has.
122 additionalProperties: false
130 - qcom,sdm845-qmp-usb3-uni-phy
135 - description: Phy aux clock.
136 - description: Phy config clock.
137 - description: 19.2 MHz ref clk.
138 - description: Phy common block aux clock.
147 - description: reset of phy block.
148 - description: phy common block reset.
158 - qcom,sdx55-qmp-usb3-uni-phy
163 - description: Phy aux clock.
164 - description: Phy config clock.
165 - description: 19.2 MHz ref clk.
173 - description: reset of phy block.
174 - description: phy common block reset.
184 - qcom,msm8996-qmp-pcie-phy
189 - description: Phy aux clock.
190 - description: Phy config clock.
191 - description: 19.2 MHz ref clk.
199 - description: reset of phy block.
200 - description: phy common block reset.
201 - description: phy's ahb cfg block reset.
212 - qcom,ipq8074-qmp-usb3-phy
213 - qcom,msm8996-qmp-usb3-phy
214 - qcom,msm8998-qmp-pcie-phy
215 - qcom,msm8998-qmp-usb3-phy
220 - description: Phy aux clock.
221 - description: Phy config clock.
222 - description: 19.2 MHz ref clk.
230 - description: reset of phy block.
231 - description: phy common block reset.
241 - qcom,msm8996-qmp-ufs-phy
246 - description: 19.2 MHz ref clk.
252 - description: PHY reset in the UFS controller.
261 - qcom,msm8998-qmp-ufs-phy
262 - qcom,sdm845-qmp-ufs-phy
263 - qcom,sm8150-qmp-ufs-phy
264 - qcom,sm8250-qmp-ufs-phy
269 - description: 19.2 MHz ref clk.
270 - description: Phy reference aux clock.
277 - description: PHY reset in the UFS controller.
286 - qcom,ipq8074-qmp-pcie-phy
291 - description: pipe clk.
297 - description: reset of phy block.
298 - description: phy common block reset.
308 - qcom,ipq6018-qmp-pcie-phy
313 - description: Phy aux clock.
314 - description: Phy config clock.
321 - description: reset of phy block.
322 - description: phy common block reset.
332 - qcom,sc8180x-qmp-pcie-phy
333 - qcom,sdm845-qhp-pcie-phy
334 - qcom,sdm845-qmp-pcie-phy
335 - qcom,sdx55-qmp-pcie-phy
336 - qcom,sm8250-qmp-gen3x1-pcie-phy
337 - qcom,sm8250-qmp-gen3x2-pcie-phy
338 - qcom,sm8250-qmp-modem-pcie-phy
343 - description: Phy aux clock.
344 - description: Phy config clock.
345 - description: 19.2 MHz ref clk.
346 - description: Phy refgen clk.
355 - description: reset of phy block.
364 - qcom,sm8150-qmp-usb3-phy
365 - qcom,sm8150-qmp-usb3-uni-phy
366 - qcom,sm8250-qmp-usb3-uni-phy
367 - qcom,sm8350-qmp-usb3-uni-phy
372 - description: Phy aux clock.
373 - description: 19.2 MHz ref clk source.
374 - description: 19.2 MHz ref clk.
375 - description: Phy common block aux clock.
384 - description: reset of phy block.
385 - description: phy common block reset.
395 - qcom,sm8250-qmp-usb3-phy
396 - qcom,sm8350-qmp-usb3-phy
401 - description: Phy aux clock.
402 - description: 19.2 MHz ref clk.
403 - description: Phy common block aux clock.
411 - description: reset of phy block.
412 - description: phy common block reset.
420 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
421 usb_2_qmpphy: phy-wrapper@88eb000 {
422 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
423 reg = <0x088eb000 0x18c>;
425 #address-cells = <1>;
427 ranges = <0x0 0x088eb000 0x2000>;
429 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK >,
430 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
431 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
432 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
433 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
435 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
436 <&gcc GCC_USB3_PHY_SEC_BCR>;
437 reset-names = "phy", "common";
439 vdda-phy-supply = <&vdda_usb2_ss_1p2>;
440 vdda-pll-supply = <&vdda_usb2_ss_core>;
442 usb_2_ssphy: phy@200 {
449 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
450 clock-names = "pipe0";
451 clock-output-names = "usb3_uni_phy_pipe_clk_src";