5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
12 <&cru SCLK_UPHY1_TCPDCORE>;
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
14 - resets : a list of phandle + reset specifier pairs
15 - reset-names : string reset name, must be:
16 "uphy", "uphy-pipe", "uphy-tcphy"
17 - extcon : extcon specifier for the Power Delivery
19 Note, there are 2 type-c phys for RK3399, and they are almost identical, except
20 these registers(description below), every register node contains 3 sections:
21 offset, enable bit, write mask bit.
22 - rockchip,typec-conn-dir : the register of type-c connector direction,
23 for type-c phy0, it must be <0xe580 0 16>;
24 for type-c phy1, it must be <0xe58c 0 16>;
25 - rockchip,usb3tousb2-en : the register of type-c force usb3 to usb2 enable
27 for type-c phy0, it must be <0xe580 3 19>;
28 for type-c phy1, it must be <0xe58c 3 19>;
29 - rockchip,external-psm : the register of type-c phy external psm clock
31 for type-c phy0, it must be <0xe588 14 30>;
32 for type-c phy1, it must be <0xe594 14 30>;
33 - rockchip,pipe-status : the register of type-c phy pipe status.
34 for type-c phy0, it must be <0xe5c0 0 0>;
35 for type-c phy1, it must be <0xe5c0 16 16>;
37 Required nodes : a sub-node is required for each port the phy provides.
38 The sub-node name is used to identify dp or usb3 port,
39 and shall be the following entries:
40 * "dp-port" : the name of DP port.
41 * "usb3-port" : the name of USB3 port.
43 Required properties (port (child) node):
44 - #phy-cells : must be 0, See ./phy-bindings.txt for details.
47 tcphy0: phy@ff7c0000 {
48 compatible = "rockchip,rk3399-typec-phy";
49 reg = <0x0 0xff7c0000 0x0 0x40000>;
50 rockchip,grf = <&grf>;
52 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
53 <&cru SCLK_UPHY0_TCPDPHY_REF>;
54 clock-names = "tcpdcore", "tcpdphy-ref";
55 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
56 assigned-clock-rates = <50000000>;
57 resets = <&cru SRST_UPHY0>,
58 <&cru SRST_UPHY0_PIPE_L00>,
59 <&cru SRST_P_UPHY0_TCPHY>;
60 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
61 rockchip,typec-conn-dir = <0xe580 0 16>;
62 rockchip,usb3tousb2-en = <0xe580 3 19>;
63 rockchip,external-psm = <0xe588 14 30>;
64 rockchip,pipe-status = <0xe5c0 0 0>;
70 tcphy0_usb3: usb3-port {
75 tcphy1: phy@ff800000 {
76 compatible = "rockchip,rk3399-typec-phy";
77 reg = <0x0 0xff800000 0x0 0x40000>;
78 rockchip,grf = <&grf>;
80 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
81 <&cru SCLK_UPHY1_TCPDPHY_REF>;
82 clock-names = "tcpdcore", "tcpdphy-ref";
83 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
84 assigned-clock-rates = <50000000>;
85 resets = <&cru SRST_UPHY1>,
86 <&cru SRST_UPHY1_PIPE_L00>,
87 <&cru SRST_P_UPHY1_TCPHY>;
88 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
89 rockchip,typec-conn-dir = <0xe58c 0 16>;
90 rockchip,usb3tousb2-en = <0xe58c 3 19>;
91 rockchip,external-psm = <0xe594 14 30>;
92 rockchip,pipe-status = <0xe5c0 16 16>;
98 tcphy1_usb3: usb3-port {