1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Cadence Torrent SD0801 PHY binding
10 This binding describes the Cadence SD0801 PHY (also known as Torrent PHY)
11 hardware included with the Cadence MHDP DisplayPort controller. Torrent
12 PHY also supports multilink multiprotocol combinations including protocols
13 such as PCIe, USB, SGMII, QSGMII etc.
16 - Swapnil Jakhade <sjakhade@cadence.com>
17 - Yuti Amonkar <yamonkar@cadence.com>
38 PHY reference clock for 1 item. Must contain an entry in clock-names.
39 Optional Parent to enable output reference clock.
45 - const: phy_en_refclk
50 assigned-clock-parents:
57 - description: Offset of the Torrent PHY configuration registers.
58 - description: Offset of the DPTX PHY configuration registers.
71 - description: Torrent PHY reset.
72 - description: Torrent APB reset. This is optional.
78 - const: torrent_reset
85 Each group of PHY lanes with a single master lane should be represented as a sub-node.
89 The master lane number. This is the lowest numbered lane in the lane group.
97 Contains list of resets, one per lane, to get all the link lanes out of reset.
104 Specifies the type of PHY for which the group of PHY lanes is used.
105 Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.
106 $ref: /schemas/types.yaml#/definitions/uint32
113 $ref: /schemas/types.yaml#/definitions/uint32
119 Specifies the Spread Spectrum Clocking mode used. It can be NO_SSC,
120 EXTERNAL_SSC or INTERNAL_SSC.
121 Refer include/dt-bindings/phy/phy-cadence.h for the constants to be used.
122 $ref: /schemas/types.yaml#/definitions/uint32
128 Maximum DisplayPort link bit rate to use, in Mbps
129 $ref: /schemas/types.yaml#/definitions/uint32
130 enum: [2160, 2430, 2700, 3240, 4320, 5400, 8100]
140 additionalProperties: false
153 additionalProperties: false
157 #include <dt-bindings/phy/phy.h>
160 #address-cells = <2>;
163 torrent-phy@f0fb500000 {
164 compatible = "cdns,torrent-phy";
165 reg = <0xf0 0xfb500000 0x0 0x00100000>,
166 <0xf0 0xfb030a00 0x0 0x00000040>;
167 reg-names = "torrent_phy", "dptx_phy";
168 resets = <&phyrst 0>;
169 reset-names = "torrent_reset";
171 clock-names = "refclk";
172 #address-cells = <1>;
176 resets = <&phyrst 1>, <&phyrst 2>,
177 <&phyrst 3>, <&phyrst 4>;
179 cdns,phy-type = <PHY_TYPE_DP>;
180 cdns,num-lanes = <4>;
181 cdns,max-bit-rate = <8100>;
186 #include <dt-bindings/phy/phy.h>
187 #include <dt-bindings/phy/phy-cadence.h>
190 #address-cells = <2>;
193 torrent-phy@f0fb500000 {
194 compatible = "cdns,torrent-phy";
195 reg = <0xf0 0xfb500000 0x0 0x00100000>;
196 reg-names = "torrent_phy";
197 resets = <&phyrst 0>, <&phyrst 1>;
198 reset-names = "torrent_reset", "torrent_apb";
200 clock-names = "refclk";
201 #address-cells = <1>;
205 resets = <&phyrst 2>, <&phyrst 3>;
207 cdns,phy-type = <PHY_TYPE_PCIE>;
208 cdns,num-lanes = <2>;
209 cdns,ssc-mode = <TORRENT_SERDES_NO_SSC>;
214 resets = <&phyrst 4>;
216 cdns,phy-type = <PHY_TYPE_SGMII>;
217 cdns,num-lanes = <1>;
218 cdns,ssc-mode = <TORRENT_SERDES_NO_SSC>;