1 Device tree binding for NVIDIA Tegra XUSB pad controller
2 ========================================================
4 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
5 signals) which connect directly to pins/pads on the SoC package. Each lane
6 is controlled by a HW block referred to as a "pad" in the Tegra hardware
7 documentation. Each such "pad" may control either one or multiple lanes,
8 and thus contains any logic common to all its lanes. Each lane can be
9 separately configured and powered up.
11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
15 ports (e.g. PCIe) and the lanes.
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
21 device tree node. Each lane exposed by the pad will be represented by its
22 own subnode and can be referenced by users of the lane using the standard
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
25 The Tegra hardware documentation refers to the connection between the XUSB
26 pad controller and the XUSB controller as "ports". This is confusing since
27 "port" is typically used to denote the physical USB receptacle. The device
28 tree binding in this document uses the term "port" to refer to the logical
29 abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
30 for the USB signal, the VBUS power supply, the USB 2.0 companion port for
31 USB 3.0 receptacles, ...).
35 - compatible: Must be:
36 - Tegra124: "nvidia,tegra124-xusb-padctl"
37 - Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl"
38 - Tegra210: "nvidia,tegra210-xusb-padctl"
39 - Tegra186: "nvidia,tegra186-xusb-padctl"
40 - reg: Physical base address and length of the controller's registers.
41 - resets: Must contain an entry for each entry in reset-names.
42 - reset-names: Must include the following entries:
46 - avdd-pll-erefeut-supply: UPHY brick and reference clock as well as UTMI PHY
47 power supply. Must supply 1.8 V.
48 - avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply
50 - vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
51 - vddio-hsic-supply: HSIC PHY power supply. Must supply 1.2 V.
57 A required child node named "pads" contains a list of subnodes, one for each
58 of the pads exposed by the XUSB pad controller. Each pad may need additional
59 resources that can be referenced in its pad node.
61 The "status" property is used to enable or disable the use of a pad. If set
62 to "disabled", the pad will not be used on the given board. In order to use
63 the pad and any of its lanes, this property must be set to "okay".
65 For Tegra124 and Tegra132, the following pads exist: usb2, ulpi, hsic, pcie
66 and sata. No extra resources are required for operation of these pads.
68 For Tegra210, the following pads exist: usb2, hsic, pcie and sata. Below is
69 a description of the properties of each pad.
75 - clocks: Must contain an entry for each entry in clock-names.
76 - clock-names: Must contain the following entries:
77 - "trk": phandle and specifier referring to the USB2 tracking clock
83 - clocks: Must contain an entry for each entry in clock-names.
84 - clock-names: Must contain the following entries:
85 - "trk": phandle and specifier referring to the HSIC tracking clock
91 - clocks: Must contain an entry for each entry in clock-names.
92 - clock-names: Must contain the following entries:
93 - "pll": phandle and specifier referring to the PLLE
94 - resets: Must contain an entry for each entry in reset-names.
95 - reset-names: Must contain the following entries:
96 - "phy": reset for the PCIe UPHY block
102 - resets: Must contain an entry for each entry in reset-names.
103 - reset-names: Must contain the following entries:
104 - "phy": reset for the SATA UPHY block
110 Each pad node has a child named "lanes" that contains one or more children of
111 its own, each representing one of the lanes controlled by the pad.
115 - status: Defines the operation status of the PHY. Valid values are:
116 - "disabled": the PHY is disabled
117 - "okay": the PHY is enabled
118 - #phy-cells: Should be 0. Since each lane represents a single PHY, there is
119 no need for an additional specifier.
120 - nvidia,function: The output function of the PHY. See below for a list of
121 valid functions per SoC generation.
123 For Tegra124 and Tegra132, the list of valid PHY nodes is given below:
124 - usb2: usb2-0, usb2-1, usb2-2
125 - functions: "snps", "xusb", "uart"
127 - functions: "snps", "xusb"
128 - hsic: hsic-0, hsic-1
129 - functions: "snps", "xusb"
130 - pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4
131 - functions: "pcie", "usb3-ss"
133 - functions: "usb3-ss", "sata"
135 For Tegra210, the list of valid PHY nodes is given below:
136 - usb2: usb2-0, usb2-1, usb2-2, usb2-3
137 - functions: "snps", "xusb", "uart"
138 - hsic: hsic-0, hsic-1
139 - functions: "snps", "xusb"
140 - pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, pcie-5, pcie-6
141 - functions: "pcie-x1", "usb3-ss", "pcie-x4"
143 - functions: "usb3-ss", "sata"
149 A required child node named "ports" contains a list of all the ports exposed
150 by the XUSB pad controller. Per-port configuration is only required for USB.
156 - status: Defines the operation status of the port. Valid values are:
157 - "disabled": the port is disabled
158 - "okay": the port is enabled
159 - mode: A string that determines the mode in which to run the port. Valid
161 - "host": for USB host mode
162 - "device": for USB device mode
163 - "otg": for USB OTG mode
166 - nvidia,internal: A boolean property whose presence determines that a port
167 is internal. In the absence of this property the port is considered to be
169 - vbus-supply: phandle to a regulator supplying the VBUS voltage.
175 - status: Defines the operation status of the port. Valid values are:
176 - "disabled": the port is disabled
177 - "okay": the port is enabled
178 - nvidia,internal: A boolean property whose presence determines that a port
179 is internal. In the absence of this property the port is considered to be
181 - vbus-supply: phandle to a regulator supplying the VBUS voltage.
187 - status: Defines the operation status of the port. Valid values are:
188 - "disabled": the port is disabled
189 - "okay": the port is enabled
192 - vbus-supply: phandle to a regulator supplying the VBUS voltage.
194 Super-speed USB ports:
195 ----------------------
198 - status: Defines the operation status of the port. Valid values are:
199 - "disabled": the port is disabled
200 - "okay": the port is enabled
201 - nvidia,usb2-companion: A single cell that specifies the physical port number
202 to map this super-speed USB port to. The range of valid port numbers varies
203 with the SoC generation:
204 - 0-2: for Tegra124 and Tegra132
208 - nvidia,internal: A boolean property whose presence determines that a port
209 is internal. In the absence of this property the port is considered to be
212 For Tegra124 and Tegra132, the XUSB pad controller exposes the following
214 - 3x USB2: usb2-0, usb2-1, usb2-2
216 - 2x HSIC: hsic-0, hsic-1
217 - 2x super-speed USB: usb3-0, usb3-1
219 For Tegra210, the XUSB pad controller exposes the following ports:
220 - 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
221 - 2x HSIC: hsic-0, hsic-1
222 - 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
228 Tegra124 and Tegra132:
229 ----------------------
235 compatible = "nvidia,tegra124-xusb-padctl";
237 compatible = "nvidia,tegra132-xusb-padctl",
238 "nvidia,tegra124-xusb-padctl";
239 reg = <0x0 0x7009f000 0x0 0x1000>;
240 resets = <&tegra_car 142>;
241 reset-names = "padctl";
381 nvidia,function = "xusb";
386 nvidia,function = "xusb";
391 nvidia,function = "xusb";
402 nvidia,function = "usb3-ss";
407 nvidia,function = "pcie";
412 nvidia,function = "pcie";
423 nvidia,function = "sata";
448 vbus-supply = <&vdd_usb3_vbus>;
464 compatible = "nvidia,tegra210-xusb-padctl";
465 reg = <0x0 0x7009f000 0x0 0x1000>;
466 resets = <&tegra_car 142>;
467 reset-names = "padctl";
473 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
501 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
519 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
521 resets = <&tegra_car 205>;
564 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
566 resets = <&tegra_car 204>;
633 nvidia,function = "xusb";
638 nvidia,function = "xusb";
643 nvidia,function = "xusb";
648 nvidia,function = "xusb";
659 nvidia,function = "pcie-x1";
664 nvidia,function = "pcie-x4";
669 nvidia,function = "pcie-x4";
674 nvidia,function = "pcie-x4";
679 nvidia,function = "pcie-x4";
684 nvidia,function = "usb3-ss";
689 nvidia,function = "usb3-ss";
700 nvidia,function = "sata";
715 vbus-supply = <&vdd_5v0_rtl>;
721 vbus-supply = <&vdd_usb_vbus>;
732 nvidia,lanes = "pcie-6";
738 nvidia,lanes = "pcie-5";