Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt

   1 Device tree binding for NVIDIA Tegra XUSB pad controller
   2 ========================================================
   3
   4 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
   5 signals) which connect directly to pins/pads on the SoC package. Each lane
   6 is controlled by a HW block referred to as a "pad" in the Tegra hardware
   7 documentation. Each such "pad" may control either one or multiple lanes,
   8 and thus contains any logic common to all its lanes. Each lane can be
   9 separately configured and powered up.
  10
  11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
  12 super-speed USB. Other lanes are for various types of low-speed, full-speed
  13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
  14 contains a software-configurable mux that sits between the I/O controller
  15 ports (e.g. PCIe) and the lanes.
  16
  17 In addition to per-lane configuration, USB 3.0 ports may require additional
  18 settings on a per-board basis.
  19
  20 Pads will be represented as children of the top-level XUSB pad controller
  21 device tree node. Each lane exposed by the pad will be represented by its
  22 own subnode and can be referenced by users of the lane using the standard
  23 PHY bindings, as described by the phy-bindings.txt file in this directory.
  24
  25 The Tegra hardware documentation refers to the connection between the XUSB
  26 pad controller and the XUSB controller as "ports". This is confusing since
  27 "port" is typically used to denote the physical USB receptacle. The device
  28 tree binding in this document uses the term "port" to refer to the logical
  29 abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
  30 for the USB signal, the VBUS power supply, the USB 2.0 companion port for
  31 USB 3.0 receptacles, ...).
  32
  33 Required properties:
  34 --------------------
  35 - compatible: Must be:
  36   - Tegra124: "nvidia,tegra124-xusb-padctl"
  37   - Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl"
  38   - Tegra210: "nvidia,tegra210-xusb-padctl"
  39   - Tegra186: "nvidia,tegra186-xusb-padctl"
  40   - Tegra194: "nvidia,tegra194-xusb-padctl"
  41 - reg: Physical base address and length of the controller's registers.
  42 - resets: Must contain an entry for each entry in reset-names.
  43 - reset-names: Must include the following entries:
  44   - "padctl"
  45
  46 For Tegra124:
  47 - avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
  48 - avdd-pll-erefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
  49 - avdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
  50 - hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 3.3 V.
  51
  52 For Tegra210:
  53 - avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
  54 - avdd-pll-uerefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
  55 - dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
  56 - hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 1.8 V.
  57 - nvidia,pmc: phandle and specifier referring to the Tegra210 PMC node.
  58
  59 For Tegra186:
  60 - avdd-pll-erefeut-supply: UPHY brick and reference clock as well as UTMI PHY
  61   power supply. Must supply 1.8 V.
  62 - avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply
  63   3.3 V.
  64 - vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
  65 - vddio-hsic-supply: HSIC PHY power supply. Must supply 1.2 V.
  66
  67 For Tegra194:
  68 - avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply
  69   3.3 V.
  70 - vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
  71
  72 Pad nodes:
  73 ==========
  74
  75 A required child node named "pads" contains a list of subnodes, one for each
  76 of the pads exposed by the XUSB pad controller. Each pad may need additional
  77 resources that can be referenced in its pad node.
  78
  79 The "status" property is used to enable or disable the use of a pad. If set
  80 to "disabled", the pad will not be used on the given board. In order to use
  81 the pad and any of its lanes, this property must be set to "okay".
  82
  83 For Tegra124 and Tegra132, the following pads exist: usb2, ulpi, hsic, pcie
  84 and sata. No extra resources are required for operation of these pads.
  85
  86 For Tegra210, the following pads exist: usb2, hsic, pcie and sata. Below is
  87 a description of the properties of each pad.
  88
  89 UTMI pad:
  90 ---------
  91
  92 Required properties:
  93 - clocks: Must contain an entry for each entry in clock-names.
  94 - clock-names: Must contain the following entries:
  95   - "trk": phandle and specifier referring to the USB2 tracking clock
  96
  97 HSIC pad:
  98 ---------
  99
 100 Required properties:
 101 - clocks: Must contain an entry for each entry in clock-names.
 102 - clock-names: Must contain the following entries:
 103   - "trk": phandle and specifier referring to the HSIC tracking clock
 104
 105 PCIe pad:
 106 ---------
 107
 108 Required properties:
 109 - clocks: Must contain an entry for each entry in clock-names.
 110 - clock-names: Must contain the following entries:
 111   - "pll": phandle and specifier referring to the PLLE
 112 - resets: Must contain an entry for each entry in reset-names.
 113 - reset-names: Must contain the following entries:
 114   - "phy": reset for the PCIe UPHY block
 115
 116 SATA pad:
 117 ---------
 118
 119 Required properties:
 120 - resets: Must contain an entry for each entry in reset-names.
 121 - reset-names: Must contain the following entries:
 122   - "phy": reset for the SATA UPHY block
 123
 124
 125 PHY nodes:
 126 ==========
 127
 128 Each pad node has a child named "lanes" that contains one or more children of
 129 its own, each representing one of the lanes controlled by the pad.
 130
 131 Required properties:
 132 --------------------
 133 - status: Defines the operation status of the PHY. Valid values are:
 134   - "disabled": the PHY is disabled
 135   - "okay": the PHY is enabled
 136 - #phy-cells: Should be 0. Since each lane represents a single PHY, there is
 137   no need for an additional specifier.
 138 - nvidia,function: The output function of the PHY. See below for a list of
 139   valid functions per SoC generation.
 140
 141 For Tegra124 and Tegra132, the list of valid PHY nodes is given below:
 142 - usb2: usb2-0, usb2-1, usb2-2
 143   - functions: "snps", "xusb", "uart"
 144 - ulpi: ulpi-0
 145   - functions: "snps", "xusb"
 146 - hsic: hsic-0, hsic-1
 147   - functions: "snps", "xusb"
 148 - pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4
 149   - functions: "pcie", "usb3-ss"
 150 - sata: sata-0
 151   - functions: "usb3-ss", "sata"
 152
 153 For Tegra210, the list of valid PHY nodes is given below:
 154 - usb2: usb2-0, usb2-1, usb2-2, usb2-3
 155   - functions: "snps", "xusb", "uart"
 156 - hsic: hsic-0, hsic-1
 157   - functions: "snps", "xusb"
 158 - pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, pcie-5, pcie-6
 159   - functions: "pcie-x1", "usb3-ss", "pcie-x4"
 160 - sata: sata-0
 161   - functions: "usb3-ss", "sata"
 162
 163 For Tegra194, the list of valid PHY nodes is given below:
 164 - usb2: usb2-0, usb2-1, usb2-2, usb2-3
 165   - functions: "xusb"
 166 - usb3: usb3-0, usb3-1, usb3-2, usb3-3
 167   - functions: "xusb"
 168
 169 Port nodes:
 170 ===========
 171
 172 A required child node named "ports" contains a list of all the ports exposed
 173 by the XUSB pad controller. Per-port configuration is only required for USB.
 174
 175 USB2 ports:
 176 -----------
 177
 178 Required properties:
 179 - status: Defines the operation status of the port. Valid values are:
 180   - "disabled": the port is disabled
 181   - "okay": the port is enabled
 182 - mode: A string that determines the mode in which to run the port. Valid
 183   values are:
 184   - "host": for USB host mode
 185   - "device": for USB device mode
 186   - "otg": for USB OTG mode
 187
 188 Required properties for OTG/Peripheral capable USB2 ports:
 189 - usb-role-switch: Boolean property to indicate that the port support OTG or
 190   peripheral mode. If present, the port supports switching between USB host
 191   and peripheral roles. Connector should be added as subnode.
 192   See usb/usb-conn-gpio.txt.
 193
 194 Optional properties:
 195 - nvidia,internal: A boolean property whose presence determines that a port
 196   is internal. In the absence of this property the port is considered to be
 197   external.
 198 - vbus-supply: phandle to a regulator supplying the VBUS voltage.
 199
 200 ULPI ports:
 201 -----------
 202
 203 Optional properties:
 204 - status: Defines the operation status of the port. Valid values are:
 205   - "disabled": the port is disabled
 206   - "okay": the port is enabled
 207 - nvidia,internal: A boolean property whose presence determines that a port
 208   is internal. In the absence of this property the port is considered to be
 209   external.
 210 - vbus-supply: phandle to a regulator supplying the VBUS voltage.
 211
 212 HSIC ports:
 213 -----------
 214
 215 Required properties:
 216 - status: Defines the operation status of the port. Valid values are:
 217   - "disabled": the port is disabled
 218   - "okay": the port is enabled
 219
 220 Optional properties:
 221 - vbus-supply: phandle to a regulator supplying the VBUS voltage.
 222
 223 Super-speed USB ports:
 224 ----------------------
 225
 226 Required properties:
 227 - status: Defines the operation status of the port. Valid values are:
 228   - "disabled": the port is disabled
 229   - "okay": the port is enabled
 230 - nvidia,usb2-companion: A single cell that specifies the physical port number
 231   to map this super-speed USB port to. The range of valid port numbers varies
 232   with the SoC generation:
 233   - 0-2: for Tegra124 and Tegra132
 234   - 0-3: for Tegra210
 235
 236 Optional properties:
 237 - nvidia,internal: A boolean property whose presence determines that a port
 238   is internal. In the absence of this property the port is considered to be
 239   external.
 240
 241 - maximum-speed: Only for Tegra194. A string property that specifies maximum
 242   supported speed of a usb3 port. Valid values are:
 243   - "super-speed-plus": default, the usb3 port supports USB 3.1 Gen 2 speed.
 244   - "super-speed": the usb3 port supports USB 3.1 Gen 1 speed only.
 245
 246 For Tegra124 and Tegra132, the XUSB pad controller exposes the following
 247 ports:
 248 - 3x USB2: usb2-0, usb2-1, usb2-2
 249 - 1x ULPI: ulpi-0
 250 - 2x HSIC: hsic-0, hsic-1
 251 - 2x super-speed USB: usb3-0, usb3-1
 252
 253 For Tegra210, the XUSB pad controller exposes the following ports:
 254 - 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
 255 - 2x HSIC: hsic-0, hsic-1
 256 - 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
 257
 258 For Tegra194, the XUSB pad controller exposes the following ports:
 259 - 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
 260 - 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
 261
 262 Examples:
 263 =========
 264
 265 Tegra124 and Tegra132:
 266 ----------------------
 267
 268 SoC include:
 269
 270         padctl@7009f000 {
 271                 /* for Tegra124 */
 272                 compatible = "nvidia,tegra124-xusb-padctl";
 273                 /* for Tegra132 */
 274                 compatible = "nvidia,tegra132-xusb-padctl",
 275                              "nvidia,tegra124-xusb-padctl";
 276                 reg = <0x0 0x7009f000 0x0 0x1000>;
 277                 resets = <&tegra_car 142>;
 278                 reset-names = "padctl";
 279
 280                 pads {
 281                         usb2 {
 282                                 status = "disabled";
 283
 284                                 lanes {
 285                                         usb2-0 {
 286                                                 status = "disabled";
 287                                                 #phy-cells = <0>;
 288                                         };
 289
 290                                         usb2-1 {
 291                                                 status = "disabled";
 292                                                 #phy-cells = <0>;
 293                                         };
 294
 295                                         usb2-2 {
 296                                                 status = "disabled";
 297                                                 #phy-cells = <0>;
 298                                         };
 299                                 };
 300                         };
 301
 302                         ulpi {
 303                                 status = "disabled";
 304
 305                                 lanes {
 306                                         ulpi-0 {
 307                                                 status = "disabled";
 308                                                 #phy-cells = <0>;
 309                                         };
 310                                 };
 311                         };
 312
 313                         hsic {
 314                                 status = "disabled";
 315
 316                                 lanes {
 317                                         hsic-0 {
 318                                                 status = "disabled";
 319                                                 #phy-cells = <0>;
 320                                         };
 321
 322                                         hsic-1 {
 323                                                 status = "disabled";
 324                                                 #phy-cells = <0>;
 325                                         };
 326                                 };
 327                         };
 328
 329                         pcie {
 330                                 status = "disabled";
 331
 332                                 lanes {
 333                                         pcie-0 {
 334                                                 status = "disabled";
 335                                                 #phy-cells = <0>;
 336                                         };
 337
 338                                         pcie-1 {
 339                                                 status = "disabled";
 340                                                 #phy-cells = <0>;
 341                                         };
 342
 343                                         pcie-2 {
 344                                                 status = "disabled";
 345                                                 #phy-cells = <0>;
 346                                         };
 347
 348                                         pcie-3 {
 349                                                 status = "disabled";
 350                                                 #phy-cells = <0>;
 351                                         };
 352
 353                                         pcie-4 {
 354                                                 status = "disabled";
 355                                                 #phy-cells = <0>;
 356                                         };
 357                                 };
 358                         };
 359
 360                         sata {
 361                                 status = "disabled";
 362
 363                                 lanes {
 364                                         sata-0 {
 365                                                 status = "disabled";
 366                                                 #phy-cells = <0>;
 367                                         };
 368                                 };
 369                         };
 370                 };
 371
 372                 ports {
 373                         usb2-0 {
 374                                 status = "disabled";
 375                         };
 376
 377                         usb2-1 {
 378                                 status = "disabled";
 379                         };
 380
 381                         usb2-2 {
 382                                 status = "disabled";
 383                         };
 384
 385                         ulpi-0 {
 386                                 status = "disabled";
 387                         };
 388
 389                         hsic-0 {
 390                                 status = "disabled";
 391                         };
 392
 393                         hsic-1 {
 394                                 status = "disabled";
 395                         };
 396
 397                         usb3-0 {
 398                                 status = "disabled";
 399                         };
 400
 401                         usb3-1 {
 402                                 status = "disabled";
 403                         };
 404                 };
 405         };
 406
 407 Board file:
 408
 409         padctl@7009f000 {
 410                 status = "okay";
 411
 412                 pads {
 413                         usb2 {
 414                                 status = "okay";
 415
 416                                 lanes {
 417                                         usb2-0 {
 418                                                 nvidia,function = "xusb";
 419                                                 status = "okay";
 420                                         };
 421
 422                                         usb2-1 {
 423                                                 nvidia,function = "xusb";
 424                                                 status = "okay";
 425                                         };
 426
 427                                         usb2-2 {
 428                                                 nvidia,function = "xusb";
 429                                                 status = "okay";
 430                                         };
 431                                 };
 432                         };
 433
 434                         pcie {
 435                                 status = "okay";
 436
 437                                 lanes {
 438                                         pcie-0 {
 439                                                 nvidia,function = "usb3-ss";
 440                                                 status = "okay";
 441                                         };
 442
 443                                         pcie-2 {
 444                                                 nvidia,function = "pcie";
 445                                                 status = "okay";
 446                                         };
 447
 448                                         pcie-4 {
 449                                                 nvidia,function = "pcie";
 450                                                 status = "okay";
 451                                         };
 452                                 };
 453                         };
 454
 455                         sata {
 456                                 status = "okay";
 457
 458                                 lanes {
 459                                         sata-0 {
 460                                                 nvidia,function = "sata";
 461                                                 status = "okay";
 462                                         };
 463                                 };
 464                         };
 465                 };
 466
 467                 ports {
 468                         /* Micro A/B */
 469                         usb2-0 {
 470                                 status = "okay";
 471                                 mode = "otg";
 472                         };
 473
 474                         /* Mini PCIe */
 475                         usb2-1 {
 476                                 status = "okay";
 477                                 mode = "host";
 478                         };
 479
 480                         /* USB3 */
 481                         usb2-2 {
 482                                 status = "okay";
 483                                 mode = "host";
 484
 485                                 vbus-supply = <&vdd_usb3_vbus>;
 486                         };
 487
 488                         usb3-0 {
 489                                 nvidia,port = <2>;
 490                                 status = "okay";
 491                         };
 492                 };
 493         };
 494
 495 Tegra210:
 496 ---------
 497
 498 SoC include:
 499
 500         padctl@7009f000 {
 501                 compatible = "nvidia,tegra210-xusb-padctl";
 502                 reg = <0x0 0x7009f000 0x0 0x1000>;
 503                 resets = <&tegra_car 142>;
 504                 reset-names = "padctl";
 505
 506                 status = "disabled";
 507
 508                 pads {
 509                         usb2 {
 510                                 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
 511                                 clock-names = "trk";
 512                                 status = "disabled";
 513
 514                                 lanes {
 515                                         usb2-0 {
 516                                                 status = "disabled";
 517                                                 #phy-cells = <0>;
 518                                         };
 519
 520                                         usb2-1 {
 521                                                 status = "disabled";
 522                                                 #phy-cells = <0>;
 523                                         };
 524
 525                                         usb2-2 {
 526                                                 status = "disabled";
 527                                                 #phy-cells = <0>;
 528                                         };
 529
 530                                         usb2-3 {
 531                                                 status = "disabled";
 532                                                 #phy-cells = <0>;
 533                                         };
 534                                 };
 535                         };
 536
 537                         hsic {
 538                                 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
 539                                 clock-names = "trk";
 540                                 status = "disabled";
 541
 542                                 lanes {
 543                                         hsic-0 {
 544                                                 status = "disabled";
 545                                                 #phy-cells = <0>;
 546                                         };
 547
 548                                         hsic-1 {
 549                                                 status = "disabled";
 550                                                 #phy-cells = <0>;
 551                                         };
 552                                 };
 553                         };
 554
 555                         pcie {
 556                                 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
 557                                 clock-names = "pll";
 558                                 resets = <&tegra_car 205>;
 559                                 reset-names = "phy";
 560                                 status = "disabled";
 561
 562                                 lanes {
 563                                         pcie-0 {
 564                                                 status = "disabled";
 565                                                 #phy-cells = <0>;
 566                                         };
 567
 568                                         pcie-1 {
 569                                                 status = "disabled";
 570                                                 #phy-cells = <0>;
 571                                         };
 572
 573                                         pcie-2 {
 574                                                 status = "disabled";
 575                                                 #phy-cells = <0>;
 576                                         };
 577
 578                                         pcie-3 {
 579                                                 status = "disabled";
 580                                                 #phy-cells = <0>;
 581                                         };
 582
 583                                         pcie-4 {
 584                                                 status = "disabled";
 585                                                 #phy-cells = <0>;
 586                                         };
 587
 588                                         pcie-5 {
 589                                                 status = "disabled";
 590                                                 #phy-cells = <0>;
 591                                         };
 592
 593                                         pcie-6 {
 594                                                 status = "disabled";
 595                                                 #phy-cells = <0>;
 596                                         };
 597                                 };
 598                         };
 599
 600                         sata {
 601                                 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
 602                                 clock-names = "pll";
 603                                 resets = <&tegra_car 204>;
 604                                 reset-names = "phy";
 605                                 status = "disabled";
 606
 607                                 lanes {
 608                                         sata-0 {
 609                                                 status = "disabled";
 610                                                 #phy-cells = <0>;
 611                                         };
 612                                 };
 613                         };
 614                 };
 615
 616                 ports {
 617                         usb2-0 {
 618                                 status = "disabled";
 619                         };
 620
 621                         usb2-1 {
 622                                 status = "disabled";
 623                         };
 624
 625                         usb2-2 {
 626                                 status = "disabled";
 627                         };
 628
 629                         usb2-3 {
 630                                 status = "disabled";
 631                         };
 632
 633                         hsic-0 {
 634                                 status = "disabled";
 635                         };
 636
 637                         hsic-1 {
 638                                 status = "disabled";
 639                         };
 640
 641                         usb3-0 {
 642                                 status = "disabled";
 643                         };
 644
 645                         usb3-1 {
 646                                 status = "disabled";
 647                         };
 648
 649                         usb3-2 {
 650                                 status = "disabled";
 651                         };
 652
 653                         usb3-3 {
 654                                 status = "disabled";
 655                         };
 656                 };
 657         };
 658
 659 Board file:
 660
 661         padctl@7009f000 {
 662                 status = "okay";
 663
 664                 pads {
 665                         usb2 {
 666                                 status = "okay";
 667
 668                                 lanes {
 669                                         usb2-0 {
 670                                                 nvidia,function = "xusb";
 671                                                 status = "okay";
 672                                         };
 673
 674                                         usb2-1 {
 675                                                 nvidia,function = "xusb";
 676                                                 status = "okay";
 677                                         };
 678
 679                                         usb2-2 {
 680                                                 nvidia,function = "xusb";
 681                                                 status = "okay";
 682                                         };
 683
 684                                         usb2-3 {
 685                                                 nvidia,function = "xusb";
 686                                                 status = "okay";
 687                                         };
 688                                 };
 689                         };
 690
 691                         pcie {
 692                                 status = "okay";
 693
 694                                 lanes {
 695                                         pcie-0 {
 696                                                 nvidia,function = "pcie-x1";
 697                                                 status = "okay";
 698                                         };
 699
 700                                         pcie-1 {
 701                                                 nvidia,function = "pcie-x4";
 702                                                 status = "okay";
 703                                         };
 704
 705                                         pcie-2 {
 706                                                 nvidia,function = "pcie-x4";
 707                                                 status = "okay";
 708                                         };
 709
 710                                         pcie-3 {
 711                                                 nvidia,function = "pcie-x4";
 712                                                 status = "okay";
 713                                         };
 714
 715                                         pcie-4 {
 716                                                 nvidia,function = "pcie-x4";
 717                                                 status = "okay";
 718                                         };
 719
 720                                         pcie-5 {
 721                                                 nvidia,function = "usb3-ss";
 722                                                 status = "okay";
 723                                         };
 724
 725                                         pcie-6 {
 726                                                 nvidia,function = "usb3-ss";
 727                                                 status = "okay";
 728                                         };
 729                                 };
 730                         };
 731
 732                         sata {
 733                                 status = "okay";
 734
 735                                 lanes {
 736                                         sata-0 {
 737                                                 nvidia,function = "sata";
 738                                                 status = "okay";
 739                                         };
 740                                 };
 741                         };
 742                 };
 743
 744                 ports {
 745                         usb2-0 {
 746                                 status = "okay";
 747                                 mode = "otg";
 748                         };
 749
 750                         usb2-1 {
 751                                 status = "okay";
 752                                 vbus-supply = <&vdd_5v0_rtl>;
 753                                 mode = "host";
 754                         };
 755
 756                         usb2-2 {
 757                                 status = "okay";
 758                                 vbus-supply = <&vdd_usb_vbus>;
 759                                 mode = "host";
 760                         };
 761
 762                         usb2-3 {
 763                                 status = "okay";
 764                                 mode = "host";
 765                         };
 766
 767                         usb3-0 {
 768                                 status = "okay";
 769                                 nvidia,lanes = "pcie-6";
 770                                 nvidia,port = <1>;
 771                         };
 772
 773                         usb3-1 {
 774                                 status = "okay";
 775                                 nvidia,lanes = "pcie-5";
 776                                 nvidia,port = <2>;
 777                         };
 778                 };
 779         };