1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (c) 2020 MediaTek
5 $id: http://devicetree.org/schemas/phy/mediatek,xsphy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek XS-PHY Controller Device Tree Bindings
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The XS-PHY controller supports physical layer functionality for USB3.1
15 GEN2 controller on MediaTek SoCs.
18 ----------------------------------
28 u31 common 0x3000 DIG_GLB
30 u31 port0 0x3400 DIG_LN_TOP
35 u31 port1 0x3a00 DIG_LN_TOP
41 DIG_GLB & PHYA_GLB are shared by U31 ports.
45 pattern: "^xs-phy@[0-9a-f]+$"
50 - mediatek,mt3611-xsphy
51 - mediatek,mt3612-xsphy
52 - const: mediatek,xsphy
56 Register shared by multiple U3 ports, exclude port's private register,
57 if only U2 ports provided, shouldn't use the property.
68 mediatek,src-ref-clk-mhz:
70 Frequency of reference clock for slew rate calibrate
75 Coefficient for slew rate calibrate, depends on SoC process
76 $ref: /schemas/types.yaml#/definitions/uint32
79 # Required child node:
81 "^usb-phy@[0-9a-f]+$":
84 A sub-node is required for each port the controller provides.
85 Address range information including the usual 'reg' property
86 is used inside these nodes to describe the controller's topology.
94 - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
103 The cells contain the following arguments.
105 - description: The PHY type
110 # The following optional vendor properties are only for debug or HQA test
113 The value of slew rate calibrate (U2 phy)
114 $ref: /schemas/types.yaml#/definitions/uint32
120 The selection of VRT reference voltage (U2 phy)
121 $ref: /schemas/types.yaml#/definitions/uint32
127 The selection of HS_TX TERM reference voltage (U2 phy)
128 $ref: /schemas/types.yaml#/definitions/uint32
134 The selection of Internal Resistor (U2/U3 phy)
135 $ref: /schemas/types.yaml#/definitions/uint32
139 mediatek,efuse-tx-imp:
141 The selection of TX Impedance (U3 phy)
142 $ref: /schemas/types.yaml#/definitions/uint32
146 mediatek,efuse-rx-imp:
148 The selection of RX Impedance (U3 phy)
149 $ref: /schemas/types.yaml#/definitions/uint32
159 additionalProperties: false
167 additionalProperties: false
171 #include <dt-bindings/phy/phy.h>
173 u3phy: xs-phy@11c40000 {
174 compatible = "mediatek,mt3611-xsphy", "mediatek,xsphy";
175 reg = <0x11c43000 0x0200>;
176 mediatek,src-ref-clk-mhz = <26>;
177 mediatek,src-coef = <17>;
178 #address-cells = <1>;
182 u2port0: usb-phy@11c40000 {
183 reg = <0x11c40000 0x0400>;
186 mediatek,eye-src = <4>;
190 u3port0: usb-phy@11c43000 {
191 reg = <0x11c43400 0x0500>;
194 mediatek,efuse-intr = <28>;