1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (c) 2020 MediaTek
5 $id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek T-PHY Controller Device Tree Bindings
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The T-PHY controller supports physical layer functionality for a number of
15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
19 -----------------------------------
24 u2 port0 0x0800 U2PHY_COM
25 u3 port0 0x0900 U3PHYD
29 u2 port1 0x1000 U2PHY_COM
30 u3 port1 0x1100 U3PHYD
34 u2 port2 0x1800 U2PHY_COM
60 SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back
61 into each port; a new bank MISC for u2 ports and CHIP for u3 ports are
62 added on V2; the FMREG bank for slew rate calibration is not used anymore
67 pattern: "^t-phy@[0-9a-f]+$"
73 - mediatek,mt2701-tphy
74 - mediatek,mt7623-tphy
75 - mediatek,mt7622-tphy
76 - mediatek,mt8516-tphy
77 - const: mediatek,generic-tphy-v1
80 - mediatek,mt2712-tphy
81 - mediatek,mt7629-tphy
82 - mediatek,mt8183-tphy
83 - const: mediatek,generic-tphy-v2
86 - mediatek,mt8195-tphy
87 - const: mediatek,generic-tphy-v3
88 - const: mediatek,mt2701-u3phy
90 - const: mediatek,mt2712-u3phy
92 - const: mediatek,mt8173-u3phy
96 Register shared by multiple ports, exclude port's private register.
97 It is needed for T-PHY V1, such as mt2701 and mt8173, but not for
98 T-PHY V2/V3, such as mt2712.
107 # Used with non-empty value if optional 'reg' is not provided.
108 # The format of the value is an arbitrary number of triplets of
109 # (child-bus-address, parent-bus-address, length).
112 mediatek,src-ref-clk-mhz:
114 Frequency of reference clock for slew rate calibrate
119 Coefficient for slew rate calibrate, depends on SoC process
120 $ref: /schemas/types.yaml#/definitions/uint32
123 # Required child node:
125 "^(usb|pcie|sata)-phy@[0-9a-f]+$":
128 A sub-node is required for each port the controller provides.
129 Address range information including the usual 'reg' property
130 is used inside these nodes to describe the controller's topology.
139 - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
140 - description: Reference clock of analog phy
142 Uses both clocks if the clock of analog and digital phys are
143 separated, otherwise uses "ref" clock only if needed.
154 The cells contain the following arguments.
156 - description: The PHY type
163 # The following optional vendor properties are only for debug or HQA test
166 The value of slew rate calibrate (U2 phy)
167 $ref: /schemas/types.yaml#/definitions/uint32
173 The selection of VRT reference voltage (U2 phy)
174 $ref: /schemas/types.yaml#/definitions/uint32
180 The selection of HS_TX TERM reference voltage (U2 phy)
181 $ref: /schemas/types.yaml#/definitions/uint32
187 The selection of internal resistor (U2 phy)
188 $ref: /schemas/types.yaml#/definitions/uint32
194 The selection of disconnect threshold (U2 phy)
195 $ref: /schemas/types.yaml#/definitions/uint32
201 Specify the flag to enable BC1.2 if support it
204 mediatek,syscon-type:
205 $ref: /schemas/types.yaml#/definitions/phandle-array
208 A phandle to syscon used to access the register of type switch,
209 the field should always be 3 cells long.
213 The first cell represents a phandle to syscon
215 The second cell represents the register offset
217 The third cell represents the index of config segment
224 additionalProperties: false
232 additionalProperties: false
236 #include <dt-bindings/clock/mt8173-clk.h>
237 #include <dt-bindings/interrupt-controller/arm-gic.h>
238 #include <dt-bindings/interrupt-controller/irq.h>
239 #include <dt-bindings/phy/phy.h>
241 compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3";
242 reg = <0x11271000 0x3000>, <0x11280700 0x0100>;
243 reg-names = "mac", "ippc";
244 phys = <&u2port0 PHY_TYPE_USB2>,
245 <&u3port0 PHY_TYPE_USB3>,
246 <&u2port1 PHY_TYPE_USB2>;
247 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
248 clocks = <&topckgen CLK_TOP_USB30_SEL>;
249 clock-names = "sys_ck";
253 compatible = "mediatek,mt8173-u3phy";
254 reg = <0x11290000 0x800>;
255 #address-cells = <1>;
259 u2port0: usb-phy@11290800 {
260 reg = <0x11290800 0x100>;
261 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>, <&clk48m>;
262 clock-names = "ref", "da_ref";
266 u3port0: usb-phy@11290900 {
267 reg = <0x11290900 0x700>;
273 u2port1: usb-phy@11291000 {
274 reg = <0x11291000 0x100>;