1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (c) 2020 MediaTek
5 $id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek T-PHY Controller Device Tree Bindings
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The T-PHY controller supports physical layer functionality for a number of
15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
18 T-PHY V2 (mt2712) when works on USB mode:
19 -----------------------------------
24 u2 port0 0x0800 U2PHY_COM
25 u3 port0 0x0900 U3PHYD
29 u2 port1 0x1000 U2PHY_COM
30 u3 port1 0x1100 U3PHYD
34 u2 port2 0x1800 U2PHY_COM
60 SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back
61 into each port; a new bank MISC for u2 ports and CHIP for u3 ports are
66 pattern: "^t-phy@[0-9a-f]+$"
72 - mediatek,mt2701-tphy
73 - mediatek,mt7623-tphy
74 - mediatek,mt7622-tphy
75 - mediatek,mt8516-tphy
76 - const: mediatek,generic-tphy-v1
79 - mediatek,mt2712-tphy
80 - mediatek,mt7629-tphy
81 - mediatek,mt8183-tphy
82 - mediatek,mt8195-tphy
83 - const: mediatek,generic-tphy-v2
84 - const: mediatek,mt2701-u3phy
86 - const: mediatek,mt2712-u3phy
88 - const: mediatek,mt8173-u3phy
92 Register shared by multiple ports, exclude port's private register.
93 It is needed for T-PHY V1, such as mt2701 and mt8173, but not for
94 T-PHY V2, such as mt2712.
103 # Used with non-empty value if optional 'reg' is not provided.
104 # The format of the value is an arbitrary number of triplets of
105 # (child-bus-address, parent-bus-address, length).
108 mediatek,src-ref-clk-mhz:
110 Frequency of reference clock for slew rate calibrate
115 Coefficient for slew rate calibrate, depends on SoC process
116 $ref: /schemas/types.yaml#/definitions/uint32
119 # Required child node:
121 "^(usb|pcie|sata)-phy@[0-9a-f]+$":
124 A sub-node is required for each port the controller provides.
125 Address range information including the usual 'reg' property
126 is used inside these nodes to describe the controller's topology.
136 - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
137 - description: Reference clock of analog phy
139 Uses both clocks if the clock of analog and digital phys are
140 separated, otherwise uses "ref" clock only if needed.
152 The cells contain the following arguments.
154 - description: The PHY type
161 # The following optional vendor properties are only for debug or HQA test
164 The value of slew rate calibrate (U2 phy)
165 $ref: /schemas/types.yaml#/definitions/uint32
171 The selection of VRT reference voltage (U2 phy)
172 $ref: /schemas/types.yaml#/definitions/uint32
178 The selection of HS_TX TERM reference voltage (U2 phy)
179 $ref: /schemas/types.yaml#/definitions/uint32
185 The selection of internal resistor (U2 phy)
186 $ref: /schemas/types.yaml#/definitions/uint32
192 The selection of disconnect threshold (U2 phy)
193 $ref: /schemas/types.yaml#/definitions/uint32
199 Specify the flag to enable BC1.2 if support it
206 additionalProperties: false
214 additionalProperties: false
218 #include <dt-bindings/clock/mt8173-clk.h>
219 #include <dt-bindings/interrupt-controller/arm-gic.h>
220 #include <dt-bindings/interrupt-controller/irq.h>
221 #include <dt-bindings/phy/phy.h>
223 compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3";
224 reg = <0x11271000 0x3000>, <0x11280700 0x0100>;
225 reg-names = "mac", "ippc";
226 phys = <&u2port0 PHY_TYPE_USB2>,
227 <&u3port0 PHY_TYPE_USB3>,
228 <&u2port1 PHY_TYPE_USB2>;
229 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
230 clocks = <&topckgen CLK_TOP_USB30_SEL>;
231 clock-names = "sys_ck";
235 compatible = "mediatek,mt8173-u3phy";
236 reg = <0x11290000 0x800>;
237 #address-cells = <1>;
241 u2port0: usb-phy@11290800 {
242 reg = <0x11290800 0x100>;
243 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>, <&clk48m>;
244 clock-names = "ref", "da_ref";
248 u3port0: usb-phy@11290900 {
249 reg = <0x11290900 0x700>;
255 u2port1: usb-phy@11291000 {
256 reg = <0x11291000 0x100>;