1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (c) 2020 MediaTek
5 $id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek High Definition Multimedia Interface (HDMI) PHY binding
11 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12 - Philipp Zabel <p.zabel@pengutronix.de>
13 - Chunfeng Yun <chunfeng.yun@mediatek.com>
16 The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
17 output and drives the HDMI pads.
21 pattern: "^hdmi-phy@[0-9a-f]+$"
27 - mediatek,mt7623-hdmi-phy
28 - const: mediatek,mt2701-hdmi-phy
29 - const: mediatek,mt2701-hdmi-phy
30 - const: mediatek,mt8173-hdmi-phy
37 - description: PLL reference clock
45 - const: hdmitx_dig_cts
55 TX DRV bias current for < 1.65Gbps
56 $ref: /schemas/types.yaml#/definitions/uint32
63 TX DRV bias current for >= 1.65Gbps
64 $ref: /schemas/types.yaml#/definitions/uint32
78 additionalProperties: false
82 #include <dt-bindings/clock/mt8173-clk.h>
83 hdmi_phy: hdmi-phy@10209100 {
84 compatible = "mediatek,mt8173-hdmi-phy";
85 reg = <0x10209100 0x24>;
86 clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
87 clock-names = "pll_ref";
88 clock-output-names = "hdmitx_dig_cts";
89 mediatek,ibias = <0xa>;
90 mediatek,ibias_up = <0x1c>;