1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8 SoC series PCIe PHY
10 - Richard Zhu <hongxing.zhu@nxp.com>
45 Specifies the mode of the refclk pad used. It can be UNUSED(PHY
46 refclock is derived from SoC internal source), INPUT(PHY refclock
47 is provided externally via the refclk pad) or OUTPUT(PHY refclock
48 is derived from SoC internal source and provided on the refclk pad).
49 Refer include/dt-bindings/phy/phy-imx8-pcie.h for the constants
51 $ref: /schemas/types.yaml#/definitions/uint32
55 description: Gen1 De-emphasis value (optional).
56 $ref: /schemas/types.yaml#/definitions/uint32
60 description: Gen2 De-emphasis value (optional).
61 $ref: /schemas/types.yaml#/definitions/uint32
64 fsl,clkreq-unsupported:
66 description: A boolean property indicating the CLKREQ# signal is
67 not supported in the board design (optional)
70 description: PCIe PHY power domain (optional).
81 additionalProperties: false
85 #include <dt-bindings/clock/imx8mm-clock.h>
86 #include <dt-bindings/phy/phy-imx8-pcie.h>
87 #include <dt-bindings/reset/imx8mq-reset.h>
89 pcie_phy: pcie-phy@32f00000 {
90 compatible = "fsl,imx8mm-pcie-phy";
91 reg = <0x32f00000 0x10000>;
92 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
94 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
95 assigned-clock-rates = <100000000>;
96 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>;
97 resets = <&src IMX8MQ_RESET_PCIEPHY>;
98 reset-names = "pciephy";
99 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;