3 PCIe DesignWare Controller
4 - compatible: Should be "ti,dra7-pcie" for RC
5 Should be "ti,dra7-pcie-ep" for EP
6 - phys : list of PHY specifiers (used by generic PHY framework)
7 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
8 number of PHYs as specified in *phys* property.
9 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
10 where <X> is the instance number of the pcie from the HW spec.
11 - num-lanes as specified in ../designware-pcie.txt
15 - reg : Two register ranges as listed in the reg-names property
16 - reg-names : The first entry must be "ti-conf" for the TI-specific registers
17 The second entry must be "rc-dbics" for the DesignWare PCIe
19 The third entry must be "config" for the PCIe configuration space
20 - interrupts : Two interrupt entries must be specified. The first one is for
21 main interrupt line and the second for MSI interrupt line.
28 interrupt-map : as specified in ../designware-pcie.txt
29 - ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument
30 should contain the register offset within syscon
31 and the 2nd argument should contain the bit field
32 for setting the bit to enable unaligned
37 - reg : Four register ranges as listed in the reg-names property
38 - reg-names : "ti-conf" for the TI-specific registers
39 "ep_dbics" for the standard configuration registers as
40 they are locally accessed within the DIF CS space
41 "ep_dbics2" for the standard configuration registers as
42 they are locally accessed within the DIF CS2 space
43 "addr_space" used to map remote RC address space
44 - interrupts : one interrupt entries must be specified for main interrupt.
45 - num-ib-windows : number of inbound address translation windows
46 - num-ob-windows : number of outbound address translation windows
47 - ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument
48 should contain the register offset within syscon
49 and the 2nd argument should contain the bit field
50 for setting the bit to enable unaligned
54 - gpios : Should be added if a GPIO line is required to drive PERST# line
56 NOTE: Two DT nodes may be added for each PCI controller; one for host
57 mode and another for device mode. So in order for PCI to
58 work in host mode, EP mode DT node should be disabled and in order to PCI to
59 work in EP mode, host mode DT node should be disabled. Host mode and EP
60 mode are mutually exclusive.
64 compatible = "simple-bus";
67 ranges = <0x51000000 0x51000000 0x3000
68 0x0 0x20000000 0x10000000>;
70 compatible = "ti,dra7-pcie";
71 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
72 reg-names = "rc_dbics", "ti_conf", "config";
73 interrupts = <0 232 0x4>, <0 233 0x4>;
77 ranges = <0x81000000 0 0 0x03000 0 0x00010000
78 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
79 #interrupt-cells = <1>;
83 phy-names = "pcie-phy0";
84 interrupt-map-mask = <0 0 0 7>;
85 interrupt-map = <0 0 0 1 &pcie_intc 1>,
86 <0 0 0 2 &pcie_intc 2>,
87 <0 0 0 3 &pcie_intc 3>,
88 <0 0 0 4 &pcie_intc 4>;
89 pcie_intc: interrupt-controller {
92 #interrupt-cells = <1>;