1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
5 $id: "http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: TI J721E PCI Host (PCIe Wrapper)
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: "cdns-pcie-host.yaml#"
19 - const: ti,j721e-pcie-host
20 - description: PCIe controller in AM64
22 - const: ti,am64-pcie-host
23 - const: ti,j721e-pcie-host
24 - description: PCIe controller in J7200
26 - const: ti,j7200-pcie-host
27 - const: ti,j721e-pcie-host
40 $ref: /schemas/types.yaml#/definitions/phandle-array
43 - description: Phandle to the SYSCON entry
44 - description: pcie_ctrl register offset within SYSCON
45 description: Specifier for configuring PCIe mode and link speed.
54 clock-specifier to represent input to the PCIe for 1 item.
55 2nd item if present represents reference clock to the connector.
96 unevaluatedProperties: false
100 #include <dt-bindings/soc/ti,sci_pm_domain.h>
101 #include <dt-bindings/gpio/gpio.h>
104 #address-cells = <2>;
107 pcie0_rc: pcie@2900000 {
108 compatible = "ti,j721e-pcie-host";
109 reg = <0x00 0x02900000 0x00 0x1000>,
110 <0x00 0x02907000 0x00 0x400>,
111 <0x00 0x0d000000 0x00 0x00800000>,
112 <0x00 0x10000000 0x00 0x00001000>;
113 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
114 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
115 max-link-speed = <3>;
117 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
118 clocks = <&k3_clks 239 1>;
121 #address-cells = <3>;
123 bus-range = <0x0 0xf>;
124 vendor-id = <0x104c>;
125 device-id = <0xb00d>;
126 msi-map = <0x0 &gic_its 0x0 0x10000>;
128 reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
129 phys = <&serdes0_pcie_link>;
130 phy-names = "pcie-phy";
131 ranges = <0x01000000 0x0 0x10001000 0x00 0x10001000 0x0 0x0010000>,
132 <0x02000000 0x0 0x10011000 0x00 0x10011000 0x0 0x7fef000>;
133 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;