Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
   3 %YAML 1.2
   4 ---
   5 $id: "http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#"
   6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
   7
   8 title: TI J721E PCI Host (PCIe Wrapper)
   9
  10 maintainers:
  11   - Kishon Vijay Abraham I <kishon@ti.com>
  12
  13 allOf:
  14   - $ref: "cdns-pcie-host.yaml#"
  15
  16 properties:
  17   compatible:
  18     oneOf:
  19       - const: ti,j721e-pcie-host
  20       - description: PCIe controller in AM64
  21         items:
  22           - const: ti,am64-pcie-host
  23           - const: ti,j721e-pcie-host
  24       - description: PCIe controller in J7200
  25         items:
  26           - const: ti,j7200-pcie-host
  27           - const: ti,j721e-pcie-host
  28
  29   reg:
  30     maxItems: 4
  31
  32   reg-names:
  33     items:
  34       - const: intd_cfg
  35       - const: user_cfg
  36       - const: reg
  37       - const: cfg
  38
  39   ti,syscon-pcie-ctrl:
  40     $ref: /schemas/types.yaml#/definitions/phandle-array
  41     items:
  42       - items:
  43           - description: Phandle to the SYSCON entry
  44           - description: pcie_ctrl register offset within SYSCON
  45     description: Specifier for configuring PCIe mode and link speed.
  46
  47   power-domains:
  48     maxItems: 1
  49
  50   clocks:
  51     minItems: 1
  52     maxItems: 2
  53     description: |+
  54       clock-specifier to represent input to the PCIe for 1 item.
  55       2nd item if present represents reference clock to the connector.
  56
  57   clock-names:
  58     minItems: 1
  59     items:
  60       - const: fck
  61       - const: pcie_refclk
  62
  63   vendor-id:
  64     const: 0x104c
  65
  66   device-id:
  67     oneOf:
  68       - items:
  69           - const: 0xb00d
  70       - items:
  71           - const: 0xb00f
  72       - items:
  73           - const: 0xb010
  74
  75   msi-map: true
  76
  77 required:
  78   - compatible
  79   - reg
  80   - reg-names
  81   - ti,syscon-pcie-ctrl
  82   - max-link-speed
  83   - num-lanes
  84   - power-domains
  85   - clocks
  86   - clock-names
  87   - vendor-id
  88   - device-id
  89   - msi-map
  90   - dma-ranges
  91   - ranges
  92   - reset-gpios
  93   - phys
  94   - phy-names
  95
  96 unevaluatedProperties: false
  97
  98 examples:
  99   - |
 100     #include <dt-bindings/soc/ti,sci_pm_domain.h>
 101     #include <dt-bindings/gpio/gpio.h>
 102
 103     bus {
 104         #address-cells = <2>;
 105         #size-cells = <2>;
 106
 107         pcie0_rc: pcie@2900000 {
 108             compatible = "ti,j721e-pcie-host";
 109             reg = <0x00 0x02900000 0x00 0x1000>,
 110                   <0x00 0x02907000 0x00 0x400>,
 111                   <0x00 0x0d000000 0x00 0x00800000>,
 112                   <0x00 0x10000000 0x00 0x00001000>;
 113             reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
 114             ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
 115             max-link-speed = <3>;
 116             num-lanes = <2>;
 117             power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
 118             clocks = <&k3_clks 239 1>;
 119             clock-names = "fck";
 120             device_type = "pci";
 121             #address-cells = <3>;
 122             #size-cells = <2>;
 123             bus-range = <0x0 0xf>;
 124             vendor-id = <0x104c>;
 125             device-id = <0xb00d>;
 126             msi-map = <0x0 &gic_its 0x0 0x10000>;
 127             dma-coherent;
 128             reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
 129             phys = <&serdes0_pcie_link>;
 130             phy-names = "pcie-phy";
 131             ranges = <0x01000000 0x0 0x10001000  0x00 0x10001000  0x0 0x0010000>,
 132                      <0x02000000 0x0 0x10011000  0x00 0x10011000  0x0 0x7fef000>;
 133             dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
 134         };
 135     };