Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
   3 %YAML 1.2
   4 ---
   5 $id: "http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#"
   6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
   7
   8 title: TI J721E PCI EP (PCIe Wrapper)
   9
  10 maintainers:
  11   - Kishon Vijay Abraham I <kishon@ti.com>
  12
  13 allOf:
  14   - $ref: "cdns-pcie-ep.yaml#"
  15
  16 properties:
  17   compatible:
  18     enum:
  19       - ti,j721e-pcie-ep
  20
  21   reg:
  22     maxItems: 4
  23
  24   reg-names:
  25     items:
  26       - const: intd_cfg
  27       - const: user_cfg
  28       - const: reg
  29       - const: mem
  30
  31   ti,syscon-pcie-ctrl:
  32     description: Phandle to the SYSCON entry required for configuring PCIe mode
  33                  and link speed.
  34     $ref: /schemas/types.yaml#/definitions/phandle
  35
  36   power-domains:
  37     maxItems: 1
  38
  39   clocks:
  40     maxItems: 1
  41     description: clock-specifier to represent input to the PCIe
  42
  43   clock-names:
  44     items:
  45       - const: fck
  46
  47   dma-coherent:
  48     description: Indicates that the PCIe IP block can ensure the coherency
  49
  50 required:
  51   - compatible
  52   - reg
  53   - reg-names
  54   - ti,syscon-pcie-ctrl
  55   - max-link-speed
  56   - num-lanes
  57   - power-domains
  58   - clocks
  59   - clock-names
  60   - cdns,max-outbound-regions
  61   - dma-coherent
  62   - max-functions
  63   - phys
  64   - phy-names
  65
  66 examples:
  67   - |
  68     #include <dt-bindings/soc/ti,sci_pm_domain.h>
  69
  70     bus {
  71         #address-cells = <2>;
  72         #size-cells = <2>;
  73
  74         pcie0_ep: pcie-ep@d000000 {
  75            compatible = "ti,j721e-pcie-ep";
  76            reg = <0x00 0x02900000 0x00 0x1000>,
  77                  <0x00 0x02907000 0x00 0x400>,
  78                  <0x00 0x0d000000 0x00 0x00800000>,
  79                  <0x00 0x10000000 0x00 0x08000000>;
  80            reg-names = "intd_cfg", "user_cfg", "reg", "mem";
  81            ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
  82            max-link-speed = <3>;
  83            num-lanes = <2>;
  84            power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
  85            clocks = <&k3_clks 239 1>;
  86            clock-names = "fck";
  87            cdns,max-outbound-regions = <16>;
  88            max-functions = /bits/ 8 <6>;
  89            dma-coherent;
  90            phys = <&serdes0_pcie_link>;
  91            phy-names = "pcie-phy";
  92        };
  93     };