1 * Renesas R-Car PCIe interface
4 compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC;
5 "renesas,pcie-r8a7744" for the R8A7744 SoC;
6 "renesas,pcie-r8a774a1" for the R8A774A1 SoC;
7 "renesas,pcie-r8a774c0" for the R8A774C0 SoC;
8 "renesas,pcie-r8a7779" for the R8A7779 SoC;
9 "renesas,pcie-r8a7790" for the R8A7790 SoC;
10 "renesas,pcie-r8a7791" for the R8A7791 SoC;
11 "renesas,pcie-r8a7793" for the R8A7793 SoC;
12 "renesas,pcie-r8a7795" for the R8A7795 SoC;
13 "renesas,pcie-r8a7796" for the R8A7796 SoC;
14 "renesas,pcie-r8a77980" for the R8A77980 SoC;
15 "renesas,pcie-r8a77990" for the R8A77990 SoC;
16 "renesas,pcie-rcar-gen2" for a generic R-Car Gen2 or
17 RZ/G1 compatible device.
18 "renesas,pcie-rcar-gen3" for a generic R-Car Gen3 or
19 RZ/G2 compatible device.
21 When compatible with the generic version, nodes must list the
22 SoC-specific version corresponding to the platform first
23 followed by the generic version.
25 - reg: base address and length of the PCIe controller registers.
26 - #address-cells: set to <3>
27 - #size-cells: set to <2>
28 - bus-range: PCI bus numbers covered
29 - device_type: set to "pci"
30 - ranges: ranges for the PCI memory and I/O regions.
31 - dma-ranges: ranges for the inbound memory regions.
32 - interrupts: two interrupt sources for MSI interrupts, followed by interrupt
33 source for hardware related interrupts (e.g. link speed change).
34 - #interrupt-cells: set to <1>
35 - interrupt-map-mask and interrupt-map: standard PCI properties
36 to define the mapping of the PCIe interface to interrupt numbers.
37 - clocks: from common clock binding: clock specifiers for the PCIe controller
39 - clock-names: from common clock binding: should be "pcie" and "pcie_bus".
42 - phys: from common PHY binding: PHY phandle and specifier (only make sense
43 for R-Car gen3 SoCs where the PCIe PHYs have their own register blocks).
44 - phy-names: from common PHY binding: should be "pcie".
48 SoC-specific DT Entry:
51 compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
52 reg = <0 0xfe000000 0 0x80000>;
55 bus-range = <0x00 0xff>;
57 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
58 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
59 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
60 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
61 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000
62 0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
63 interrupts = <0 116 4>, <0 117 4>, <0 118 4>;
64 #interrupt-cells = <1>;
65 interrupt-map-mask = <0 0 0 0>;
66 interrupt-map = <0 0 0 0 &gic 0 116 4>;
67 clocks = <&mstp3_clks R8A7791_CLK_PCIE>, <&pcie_bus_clk>;
68 clock-names = "pcie", "pcie_bus";