1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm PCI express root complex
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
26 - qcom,pcie-ipq8064-v2
28 - qcom,pcie-ipq8074-gen3
34 - const: qcom,pcie-msm8998
35 - const: qcom,pcie-msm8996
57 # Common definitions for clocks, clock-names and reset.
58 # Platform constraints are described later.
86 description: A phandle to the core analog power supply
89 description: A phandle to the core analog power supply for PHY
92 description: A phandle to the core analog power supply for IC which generates reference clock
105 description: GPIO controlled connection to PERST# signal
112 description: GPIO controlled connection to WAKE# signal
133 - $ref: /schemas/pci/pci-bus.yaml#
142 - qcom,pcie-ipq8064v2
152 - const: dbi # DesignWare PCIe registers
153 - const: elbi # External local bus interface registers
154 - const: parf # Qualcomm specific registers
155 - const: config # PCIe configuration space
163 - qcom,pcie-ipq8074-gen3
171 - const: dbi # DesignWare PCIe registers
172 - const: elbi # External local bus interface registers
173 - const: atu # ATU address space
174 - const: parf # Qualcomm specific registers
175 - const: config # PCIe configuration space
193 - const: parf # Qualcomm specific registers
194 - const: dbi # DesignWare PCIe registers
195 - const: elbi # External local bus interface registers
196 - const: config # PCIe configuration space
197 - const: mhi # MHI registers
213 - const: parf # Qualcomm specific registers
214 - const: dbi # DesignWare PCIe registers
215 - const: elbi # External local bus interface registers
216 - const: atu # ATU address space
217 - const: config # PCIe configuration space
218 - const: mhi # MHI registers
227 - qcom,pcie-ipq8064v2
236 - const: core # Clocks the pcie hw block
237 - const: iface # Configuration AHB clock
238 - const: phy # Clocks the pcie PHY block
239 - const: aux # Clocks the pcie AUX block, not on apq8064
240 - const: ref # Clocks the pcie ref block, not on apq8064
247 - const: axi # AXI reset
248 - const: ahb # AHB reset
249 - const: por # POR reset
250 - const: pci # PCI reset
251 - const: phy # PHY reset
252 - const: ext # EXT reset, not on apq8064
271 - const: iface # Configuration AHB clock
272 - const: master_bus # Master AXI clock
273 - const: slave_bus # Slave AXI clock
274 - const: aux # Auxiliary (AUX) clock
279 - const: core # Core reset
294 - const: aux # Auxiliary (AUX) clock
295 - const: master_bus # Master AXI clock
296 - const: slave_bus # Slave AXI clock
302 - const: axi_m # AXI master reset
303 - const: axi_s # AXI slave reset
304 - const: pipe # PIPE reset
305 - const: axi_m_vmid # VMID reset
306 - const: axi_s_xpu # XPU reset
307 - const: parf # PARF reset
308 - const: phy # PHY reset
309 - const: axi_m_sticky # AXI sticky reset
310 - const: pipe_sticky # PIPE sticky reset
311 - const: pwr # PWR reset
312 - const: ahb # AHB reset
313 - const: phy_ahb # PHY AHB reset
328 - const: pipe # Pipe Clock driving internal logic
329 - const: aux # Auxiliary (AUX) clock
330 - const: cfg # Configuration clock
331 - const: bus_master # Master AXI clock
332 - const: bus_slave # Slave AXI clock
349 - const: iface # PCIe to SysNOC BIU clock
350 - const: axi_m # AXI Master clock
351 - const: axi_s # AXI Slave clock
352 - const: ahb # AHB clock
353 - const: aux # Auxiliary clock
359 - const: pipe # PIPE reset
360 - const: sleep # Sleep reset
361 - const: sticky # Core Sticky reset
362 - const: axi_m # AXI Master reset
363 - const: axi_s # AXI Slave reset
364 - const: ahb # AHB Reset
365 - const: axi_m_sticky # AXI Master Sticky reset
373 - qcom,pcie-ipq8074-gen3
381 - const: iface # PCIe to SysNOC BIU clock
382 - const: axi_m # AXI Master clock
383 - const: axi_s # AXI Slave clock
384 - const: axi_bridge # AXI bridge clock
391 - const: pipe # PIPE reset
392 - const: sleep # Sleep reset
393 - const: sticky # Core Sticky reset
394 - const: axi_m # AXI Master reset
395 - const: axi_s # AXI Slave reset
396 - const: ahb # AHB Reset
397 - const: axi_m_sticky # AXI Master Sticky reset
398 - const: axi_s_sticky # AXI Slave Sticky reset
413 - const: iface # AHB clock
414 - const: aux # Auxiliary clock
415 - const: master_bus # AXI Master clock
416 - const: slave_bus # AXI Slave clock
422 - const: axi_m # AXI Master reset
423 - const: axi_s # AXI Slave reset
424 - const: axi_m_sticky # AXI Master Sticky reset
425 - const: pipe_sticky # PIPE sticky reset
426 - const: pwr # PWR reset
427 - const: ahb # AHB reset
437 # Unfortunately the "optional" ref clock is used in the middle of the list
444 - const: pipe # PIPE clock
445 - const: aux # Auxiliary clock
446 - const: cfg # Configuration clock
447 - const: bus_master # Master AXI clock
448 - const: bus_slave # Slave AXI clock
449 - const: slave_q2a # Slave Q2A clock
450 - const: ref # REFERENCE clock
451 - const: tbu # PCIe TBU clock
458 - const: pipe # PIPE clock
459 - const: aux # Auxiliary clock
460 - const: cfg # Configuration clock
461 - const: bus_master # Master AXI clock
462 - const: bus_slave # Slave AXI clock
463 - const: slave_q2a # Slave Q2A clock
464 - const: tbu # PCIe TBU clock
470 - const: pci # PCIe core reset
485 - const: pipe # PIPE clock
486 - const: aux # Auxiliary clock
487 - const: cfg # Configuration clock
488 - const: bus_master # Master AXI clock
489 - const: bus_slave # Slave AXI clock
490 - const: slave_q2a # Slave Q2A clock
491 - const: sleep # PCIe Sleep clock
496 - const: pci # PCIe core reset
507 - qcom,pcie-ipq8064v2
509 - qcom,pcie-ipq8074-gen3
566 - qcom,pcie-ipq8064-v2
568 - qcom,pcie-ipq8074-gen3
578 unevaluatedProperties: false
582 #include <dt-bindings/interrupt-controller/arm-gic.h>
584 compatible = "qcom,pcie-ipq8064";
585 reg = <0x1b500000 0x1000>,
588 <0x0ff00000 0x100000>;
589 reg-names = "dbi", "elbi", "parf", "config";
591 linux,pci-domain = <0>;
592 bus-range = <0x00 0xff>;
594 #address-cells = <3>;
596 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>,
597 <0x82000000 0 0 0x08000000 0 0x07e00000>;
598 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
599 interrupt-names = "msi";
600 #interrupt-cells = <1>;
601 interrupt-map-mask = <0 0 0 0x7>;
602 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>,
603 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>,
604 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>,
605 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>;
611 clock-names = "core", "iface", "phy", "aux", "ref";
618 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
619 pinctrl-0 = <&pcie_pins_default>;
620 pinctrl-names = "default";
621 vdda-supply = <&pm8921_s3>;
622 vdda_phy-supply = <&pm8921_lvs6>;
623 vdda_refclk-supply = <&ext_3p3v>;
626 #include <dt-bindings/interrupt-controller/arm-gic.h>
627 #include <dt-bindings/gpio/gpio.h>
629 compatible = "qcom,pcie-apq8084";
630 reg = <0xfc520000 0x2000>,
634 reg-names = "parf", "dbi", "elbi", "config";
636 linux,pci-domain = <0>;
637 bus-range = <0x00 0xff>;
639 #address-cells = <3>;
641 ranges = <0x81000000 0 0 0xff200000 0 0x00100000>,
642 <0x82000000 0 0x00300000 0xff300000 0 0x00d00000>;
643 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
644 interrupt-names = "msi";
645 #interrupt-cells = <1>;
646 interrupt-map-mask = <0 0 0 0x7>;
647 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>,
648 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>,
649 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>,
650 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>;
655 clock-names = "iface", "master_bus", "slave_bus", "aux";
657 reset-names = "core";
658 power-domains = <&gcc 1>;
659 vdda-supply = <&pma8084_l3>;
661 phy-names = "pciephy";
662 perst-gpios = <&tlmm 70 GPIO_ACTIVE_LOW>;
663 pinctrl-0 = <&pcie0_pins_default>;
664 pinctrl-names = "default";