1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm PCI express root complex
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
26 - qcom,pcie-ipq8064-v2
28 - qcom,pcie-ipq8074-gen3
41 - qcom,pcie-sm8450-pcie0
42 - qcom,pcie-sm8450-pcie1
45 - const: qcom,pcie-msm8998
46 - const: qcom,pcie-msm8996
68 # Common definitions for clocks, clock-names and reset.
69 # Platform constraints are described later.
97 description: A phandle to the core analog power supply
100 description: A phandle to the core analog power supply for PHY
103 description: A phandle to the core analog power supply for IC which generates reference clock
106 description: A phandle to the PCIe endpoint power supply
119 description: GPIO controlled connection to PERST# signal
123 description: GPIO controlled connection to WAKE# signal
145 - $ref: /schemas/pci/pci-bus.yaml#
154 - qcom,pcie-ipq8064v2
164 - const: dbi # DesignWare PCIe registers
165 - const: elbi # External local bus interface registers
166 - const: parf # Qualcomm specific registers
167 - const: config # PCIe configuration space
175 - qcom,pcie-ipq8074-gen3
183 - const: dbi # DesignWare PCIe registers
184 - const: elbi # External local bus interface registers
185 - const: atu # ATU address space
186 - const: parf # Qualcomm specific registers
187 - const: config # PCIe configuration space
205 - const: parf # Qualcomm specific registers
206 - const: dbi # DesignWare PCIe registers
207 - const: elbi # External local bus interface registers
208 - const: config # PCIe configuration space
209 - const: mhi # MHI registers
223 - qcom,pcie-sm8450-pcie0
224 - qcom,pcie-sm8450-pcie1
234 - const: parf # Qualcomm specific registers
235 - const: dbi # DesignWare PCIe registers
236 - const: elbi # External local bus interface registers
237 - const: atu # ATU address space
238 - const: config # PCIe configuration space
239 - const: mhi # MHI registers
248 - qcom,pcie-ipq8064v2
257 - const: core # Clocks the pcie hw block
258 - const: iface # Configuration AHB clock
259 - const: phy # Clocks the pcie PHY block
260 - const: aux # Clocks the pcie AUX block, not on apq8064
261 - const: ref # Clocks the pcie ref block, not on apq8064
268 - const: axi # AXI reset
269 - const: ahb # AHB reset
270 - const: por # POR reset
271 - const: pci # PCI reset
272 - const: phy # PHY reset
273 - const: ext # EXT reset, not on apq8064
292 - const: iface # Configuration AHB clock
293 - const: master_bus # Master AXI clock
294 - const: slave_bus # Slave AXI clock
295 - const: aux # Auxiliary (AUX) clock
300 - const: core # Core reset
315 - const: aux # Auxiliary (AUX) clock
316 - const: master_bus # Master AXI clock
317 - const: slave_bus # Slave AXI clock
323 - const: axi_m # AXI master reset
324 - const: axi_s # AXI slave reset
325 - const: pipe # PIPE reset
326 - const: axi_m_vmid # VMID reset
327 - const: axi_s_xpu # XPU reset
328 - const: parf # PARF reset
329 - const: phy # PHY reset
330 - const: axi_m_sticky # AXI sticky reset
331 - const: pipe_sticky # PIPE sticky reset
332 - const: pwr # PWR reset
333 - const: ahb # AHB reset
334 - const: phy_ahb # PHY AHB reset
349 - const: pipe # Pipe Clock driving internal logic
350 - const: aux # Auxiliary (AUX) clock
351 - const: cfg # Configuration clock
352 - const: bus_master # Master AXI clock
353 - const: bus_slave # Slave AXI clock
370 - const: iface # PCIe to SysNOC BIU clock
371 - const: axi_m # AXI Master clock
372 - const: axi_s # AXI Slave clock
373 - const: ahb # AHB clock
374 - const: aux # Auxiliary clock
380 - const: pipe # PIPE reset
381 - const: sleep # Sleep reset
382 - const: sticky # Core Sticky reset
383 - const: axi_m # AXI Master reset
384 - const: axi_s # AXI Slave reset
385 - const: ahb # AHB Reset
386 - const: axi_m_sticky # AXI Master Sticky reset
394 - qcom,pcie-ipq8074-gen3
402 - const: iface # PCIe to SysNOC BIU clock
403 - const: axi_m # AXI Master clock
404 - const: axi_s # AXI Slave clock
405 - const: axi_bridge # AXI bridge clock
412 - const: pipe # PIPE reset
413 - const: sleep # Sleep reset
414 - const: sticky # Core Sticky reset
415 - const: axi_m # AXI Master reset
416 - const: axi_s # AXI Slave reset
417 - const: ahb # AHB Reset
418 - const: axi_m_sticky # AXI Master Sticky reset
419 - const: axi_s_sticky # AXI Slave Sticky reset
434 - const: iface # AHB clock
435 - const: aux # Auxiliary clock
436 - const: master_bus # AXI Master clock
437 - const: slave_bus # AXI Slave clock
443 - const: axi_m # AXI Master reset
444 - const: axi_s # AXI Slave reset
445 - const: axi_m_sticky # AXI Master Sticky reset
446 - const: pipe_sticky # PIPE sticky reset
447 - const: pwr # PWR reset
448 - const: ahb # AHB reset
463 - const: pipe # PIPE clock
464 - const: pipe_mux # PIPE MUX
465 - const: phy_pipe # PIPE output clock
466 - const: ref # REFERENCE clock
467 - const: aux # Auxiliary clock
468 - const: cfg # Configuration clock
469 - const: bus_master # Master AXI clock
470 - const: bus_slave # Slave AXI clock
471 - const: slave_q2a # Slave Q2A clock
472 - const: tbu # PCIe TBU clock
473 - const: ddrss_sf_tbu # PCIe SF TBU clock
474 - const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock
475 - const: aggre1 # Aggre NoC PCIe1 AXI clock
480 - const: pci # PCIe core reset
495 - const: pipe # PIPE clock
496 - const: aux # Auxiliary clock
497 - const: cfg # Configuration clock
498 - const: bus_master # Master AXI clock
499 - const: bus_slave # Slave AXI clock
500 - const: slave_q2a # Slave Q2A clock
501 - const: ref # REFERENCE clock
502 - const: tbu # PCIe TBU clock
507 - const: pci # PCIe core reset
517 # Unfortunately the "optional" ref clock is used in the middle of the list
524 - const: pipe # PIPE clock
525 - const: aux # Auxiliary clock
526 - const: cfg # Configuration clock
527 - const: bus_master # Master AXI clock
528 - const: bus_slave # Slave AXI clock
529 - const: slave_q2a # Slave Q2A clock
530 - const: ref # REFERENCE clock
531 - const: tbu # PCIe TBU clock
538 - const: pipe # PIPE clock
539 - const: aux # Auxiliary clock
540 - const: cfg # Configuration clock
541 - const: bus_master # Master AXI clock
542 - const: bus_slave # Slave AXI clock
543 - const: slave_q2a # Slave Q2A clock
544 - const: tbu # PCIe TBU clock
550 - const: pci # PCIe core reset
561 # Unfortunately the "optional" ref clock is used in the middle of the list
568 - const: pipe # PIPE clock
569 - const: aux # Auxiliary clock
570 - const: cfg # Configuration clock
571 - const: bus_master # Master AXI clock
572 - const: bus_slave # Slave AXI clock
573 - const: slave_q2a # Slave Q2A clock
574 - const: ref # REFERENCE clock
575 - const: tbu # PCIe TBU clock
576 - const: ddrss_sf_tbu # PCIe SF TBU clock
583 - const: pipe # PIPE clock
584 - const: aux # Auxiliary clock
585 - const: cfg # Configuration clock
586 - const: bus_master # Master AXI clock
587 - const: bus_slave # Slave AXI clock
588 - const: slave_q2a # Slave Q2A clock
589 - const: tbu # PCIe TBU clock
590 - const: ddrss_sf_tbu # PCIe SF TBU clock
596 - const: pci # PCIe core reset
612 - const: aux # Auxiliary clock
613 - const: cfg # Configuration clock
614 - const: bus_master # Master AXI clock
615 - const: bus_slave # Slave AXI clock
616 - const: slave_q2a # Slave Q2A clock
617 - const: tbu # PCIe TBU clock
618 - const: ddrss_sf_tbu # PCIe SF TBU clock
619 - const: aggre1 # Aggre NoC PCIe1 AXI clock
620 - const: aggre0 # Aggre NoC PCIe0 AXI clock
625 - const: pci # PCIe core reset
632 - qcom,pcie-sm8450-pcie0
640 - const: pipe # PIPE clock
641 - const: pipe_mux # PIPE MUX
642 - const: phy_pipe # PIPE output clock
643 - const: ref # REFERENCE clock
644 - const: aux # Auxiliary clock
645 - const: cfg # Configuration clock
646 - const: bus_master # Master AXI clock
647 - const: bus_slave # Slave AXI clock
648 - const: slave_q2a # Slave Q2A clock
649 - const: ddrss_sf_tbu # PCIe SF TBU clock
650 - const: aggre0 # Aggre NoC PCIe0 AXI clock
651 - const: aggre1 # Aggre NoC PCIe1 AXI clock
656 - const: pci # PCIe core reset
663 - qcom,pcie-sm8450-pcie1
671 - const: pipe # PIPE clock
672 - const: pipe_mux # PIPE MUX
673 - const: phy_pipe # PIPE output clock
674 - const: ref # REFERENCE clock
675 - const: aux # Auxiliary clock
676 - const: cfg # Configuration clock
677 - const: bus_master # Master AXI clock
678 - const: bus_slave # Slave AXI clock
679 - const: slave_q2a # Slave Q2A clock
680 - const: ddrss_sf_tbu # PCIe SF TBU clock
681 - const: aggre1 # Aggre NoC PCIe1 AXI clock
686 - const: pci # PCIe core reset
702 - const: aux # Auxiliary clock
703 - const: cfg # Configuration clock
704 - const: bus_master # Master AXI clock
705 - const: bus_slave # Slave AXI clock
706 - const: slave_q2a # Slave Q2A clock
707 - const: ddrss_sf_tbu # PCIe SF TBU clock
708 - const: noc_aggr # Aggre NoC PCIe AXI clock
709 - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock
716 - const: pci # PCIe core reset
717 - const: link_down # PCIe link down reset
734 - const: aux # Auxiliary clock
735 - const: cfg # Configuration clock
736 - const: bus_master # Master AXI clock
737 - const: bus_slave # Slave AXI clock
738 - const: slave_q2a # Slave Q2A clock
739 - const: ddrss_sf_tbu # PCIe SF TBU clock
740 - const: noc_aggr_4 # NoC aggregate 4 clock
741 - const: noc_aggr_south_sf # NoC aggregate South SF clock
742 - const: cnoc_qx # Configuration NoC QX clock
747 - const: pci # PCIe core reset
762 - const: pipe # PIPE clock
763 - const: aux # Auxiliary clock
764 - const: cfg # Configuration clock
765 - const: bus_master # Master AXI clock
766 - const: bus_slave # Slave AXI clock
767 - const: slave_q2a # Slave Q2A clock
768 - const: sleep # PCIe Sleep clock
773 - const: pci # PCIe core reset
788 - const: aux # Auxiliary clock
789 - const: cfg # Configuration clock
790 - const: bus_master # Master AXI clock
791 - const: bus_slave # Slave AXI clock
792 - const: slave_q2a # Slave Q2A clock
797 - const: pci # PCIe core reset
821 - qcom,pcie-ipq8064v2
823 - qcom,pcie-ipq8074-gen3
854 - qcom,pcie-sm8450-pcie0
855 - qcom,pcie-sm8450-pcie1
907 - qcom,pcie-ipq8064-v2
909 - qcom,pcie-ipq8074-gen3
920 unevaluatedProperties: false
924 #include <dt-bindings/interrupt-controller/arm-gic.h>
926 compatible = "qcom,pcie-ipq8064";
927 reg = <0x1b500000 0x1000>,
930 <0x0ff00000 0x100000>;
931 reg-names = "dbi", "elbi", "parf", "config";
933 linux,pci-domain = <0>;
934 bus-range = <0x00 0xff>;
936 #address-cells = <3>;
938 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>,
939 <0x82000000 0 0 0x08000000 0 0x07e00000>;
940 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
941 interrupt-names = "msi";
942 #interrupt-cells = <1>;
943 interrupt-map-mask = <0 0 0 0x7>;
944 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>,
945 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>,
946 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>,
947 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>;
953 clock-names = "core", "iface", "phy", "aux", "ref";
960 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
961 pinctrl-0 = <&pcie_pins_default>;
962 pinctrl-names = "default";
963 vdda-supply = <&pm8921_s3>;
964 vdda_phy-supply = <&pm8921_lvs6>;
965 vdda_refclk-supply = <&ext_3p3v>;
968 #include <dt-bindings/interrupt-controller/arm-gic.h>
969 #include <dt-bindings/gpio/gpio.h>
971 compatible = "qcom,pcie-apq8084";
972 reg = <0xfc520000 0x2000>,
976 reg-names = "parf", "dbi", "elbi", "config";
978 linux,pci-domain = <0>;
979 bus-range = <0x00 0xff>;
981 #address-cells = <3>;
983 ranges = <0x81000000 0 0 0xff200000 0 0x00100000>,
984 <0x82000000 0 0x00300000 0xff300000 0 0x00d00000>;
985 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
986 interrupt-names = "msi";
987 #interrupt-cells = <1>;
988 interrupt-map-mask = <0 0 0 0x7>;
989 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>,
990 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>,
991 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>,
992 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>;
997 clock-names = "iface", "master_bus", "slave_bus", "aux";
999 reset-names = "core";
1000 power-domains = <&gcc 1>;
1001 vdda-supply = <&pma8084_l3>;
1003 phy-names = "pciephy";
1004 perst-gpios = <&tlmm 70 GPIO_ACTIVE_LOW>;
1005 pinctrl-0 = <&pcie0_pins_default>;
1006 pinctrl-names = "default";