1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm PCI express root complex
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
26 - qcom,pcie-ipq8064-v2
28 - qcom,pcie-ipq8074-gen3
40 - qcom,pcie-sm8450-pcie0
41 - qcom,pcie-sm8450-pcie1
44 - const: qcom,pcie-msm8998
45 - const: qcom,pcie-msm8996
66 # Common definitions for clocks, clock-names and reset.
67 # Platform constraints are described later.
95 description: A phandle to the core analog power supply
98 description: A phandle to the core analog power supply for PHY
101 description: A phandle to the core analog power supply for IC which generates reference clock
104 description: A phandle to the PCIe endpoint power supply
117 description: GPIO controlled connection to PERST# signal
121 description: GPIO controlled connection to WAKE# signal
143 - $ref: /schemas/pci/pci-bus.yaml#
152 - qcom,pcie-ipq8064v2
162 - const: dbi # DesignWare PCIe registers
163 - const: elbi # External local bus interface registers
164 - const: parf # Qualcomm specific registers
165 - const: config # PCIe configuration space
173 - qcom,pcie-ipq8074-gen3
181 - const: dbi # DesignWare PCIe registers
182 - const: elbi # External local bus interface registers
183 - const: atu # ATU address space
184 - const: parf # Qualcomm specific registers
185 - const: config # PCIe configuration space
203 - const: parf # Qualcomm specific registers
204 - const: dbi # DesignWare PCIe registers
205 - const: elbi # External local bus interface registers
206 - const: config # PCIe configuration space
207 - const: mhi # MHI registers
220 - qcom,pcie-sm8450-pcie0
221 - qcom,pcie-sm8450-pcie1
231 - const: parf # Qualcomm specific registers
232 - const: dbi # DesignWare PCIe registers
233 - const: elbi # External local bus interface registers
234 - const: atu # ATU address space
235 - const: config # PCIe configuration space
236 - const: mhi # MHI registers
245 - qcom,pcie-ipq8064v2
254 - const: core # Clocks the pcie hw block
255 - const: iface # Configuration AHB clock
256 - const: phy # Clocks the pcie PHY block
257 - const: aux # Clocks the pcie AUX block, not on apq8064
258 - const: ref # Clocks the pcie ref block, not on apq8064
265 - const: axi # AXI reset
266 - const: ahb # AHB reset
267 - const: por # POR reset
268 - const: pci # PCI reset
269 - const: phy # PHY reset
270 - const: ext # EXT reset, not on apq8064
289 - const: iface # Configuration AHB clock
290 - const: master_bus # Master AXI clock
291 - const: slave_bus # Slave AXI clock
292 - const: aux # Auxiliary (AUX) clock
297 - const: core # Core reset
312 - const: aux # Auxiliary (AUX) clock
313 - const: master_bus # Master AXI clock
314 - const: slave_bus # Slave AXI clock
320 - const: axi_m # AXI master reset
321 - const: axi_s # AXI slave reset
322 - const: pipe # PIPE reset
323 - const: axi_m_vmid # VMID reset
324 - const: axi_s_xpu # XPU reset
325 - const: parf # PARF reset
326 - const: phy # PHY reset
327 - const: axi_m_sticky # AXI sticky reset
328 - const: pipe_sticky # PIPE sticky reset
329 - const: pwr # PWR reset
330 - const: ahb # AHB reset
331 - const: phy_ahb # PHY AHB reset
346 - const: pipe # Pipe Clock driving internal logic
347 - const: aux # Auxiliary (AUX) clock
348 - const: cfg # Configuration clock
349 - const: bus_master # Master AXI clock
350 - const: bus_slave # Slave AXI clock
367 - const: iface # PCIe to SysNOC BIU clock
368 - const: axi_m # AXI Master clock
369 - const: axi_s # AXI Slave clock
370 - const: ahb # AHB clock
371 - const: aux # Auxiliary clock
377 - const: pipe # PIPE reset
378 - const: sleep # Sleep reset
379 - const: sticky # Core Sticky reset
380 - const: axi_m # AXI Master reset
381 - const: axi_s # AXI Slave reset
382 - const: ahb # AHB Reset
383 - const: axi_m_sticky # AXI Master Sticky reset
391 - qcom,pcie-ipq8074-gen3
399 - const: iface # PCIe to SysNOC BIU clock
400 - const: axi_m # AXI Master clock
401 - const: axi_s # AXI Slave clock
402 - const: axi_bridge # AXI bridge clock
409 - const: pipe # PIPE reset
410 - const: sleep # Sleep reset
411 - const: sticky # Core Sticky reset
412 - const: axi_m # AXI Master reset
413 - const: axi_s # AXI Slave reset
414 - const: ahb # AHB Reset
415 - const: axi_m_sticky # AXI Master Sticky reset
416 - const: axi_s_sticky # AXI Slave Sticky reset
431 - const: iface # AHB clock
432 - const: aux # Auxiliary clock
433 - const: master_bus # AXI Master clock
434 - const: slave_bus # AXI Slave clock
440 - const: axi_m # AXI Master reset
441 - const: axi_s # AXI Slave reset
442 - const: axi_m_sticky # AXI Master Sticky reset
443 - const: pipe_sticky # PIPE sticky reset
444 - const: pwr # PWR reset
445 - const: ahb # AHB reset
460 - const: pipe # PIPE clock
461 - const: pipe_mux # PIPE MUX
462 - const: phy_pipe # PIPE output clock
463 - const: ref # REFERENCE clock
464 - const: aux # Auxiliary clock
465 - const: cfg # Configuration clock
466 - const: bus_master # Master AXI clock
467 - const: bus_slave # Slave AXI clock
468 - const: slave_q2a # Slave Q2A clock
469 - const: tbu # PCIe TBU clock
470 - const: ddrss_sf_tbu # PCIe SF TBU clock
471 - const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock
472 - const: aggre1 # Aggre NoC PCIe1 AXI clock
477 - const: pci # PCIe core reset
487 # Unfortunately the "optional" ref clock is used in the middle of the list
494 - const: pipe # PIPE clock
495 - const: aux # Auxiliary clock
496 - const: cfg # Configuration clock
497 - const: bus_master # Master AXI clock
498 - const: bus_slave # Slave AXI clock
499 - const: slave_q2a # Slave Q2A clock
500 - const: ref # REFERENCE clock
501 - const: tbu # PCIe TBU clock
508 - const: pipe # PIPE clock
509 - const: aux # Auxiliary clock
510 - const: cfg # Configuration clock
511 - const: bus_master # Master AXI clock
512 - const: bus_slave # Slave AXI clock
513 - const: slave_q2a # Slave Q2A clock
514 - const: tbu # PCIe TBU clock
520 - const: pci # PCIe core reset
532 # Unfortunately the "optional" ref clock is used in the middle of the list
539 - const: pipe # PIPE clock
540 - const: aux # Auxiliary clock
541 - const: cfg # Configuration clock
542 - const: bus_master # Master AXI clock
543 - const: bus_slave # Slave AXI clock
544 - const: slave_q2a # Slave Q2A clock
545 - const: ref # REFERENCE clock
546 - const: tbu # PCIe TBU clock
547 - const: ddrss_sf_tbu # PCIe SF TBU clock
554 - const: pipe # PIPE clock
555 - const: aux # Auxiliary clock
556 - const: cfg # Configuration clock
557 - const: bus_master # Master AXI clock
558 - const: bus_slave # Slave AXI clock
559 - const: slave_q2a # Slave Q2A clock
560 - const: tbu # PCIe TBU clock
561 - const: ddrss_sf_tbu # PCIe SF TBU clock
567 - const: pci # PCIe core reset
583 - const: aux # Auxiliary clock
584 - const: cfg # Configuration clock
585 - const: bus_master # Master AXI clock
586 - const: bus_slave # Slave AXI clock
587 - const: slave_q2a # Slave Q2A clock
588 - const: tbu # PCIe TBU clock
589 - const: ddrss_sf_tbu # PCIe SF TBU clock
590 - const: aggre1 # Aggre NoC PCIe1 AXI clock
591 - const: aggre0 # Aggre NoC PCIe0 AXI clock
596 - const: pci # PCIe core reset
603 - qcom,pcie-sm8450-pcie0
611 - const: pipe # PIPE clock
612 - const: pipe_mux # PIPE MUX
613 - const: phy_pipe # PIPE output clock
614 - const: ref # REFERENCE clock
615 - const: aux # Auxiliary clock
616 - const: cfg # Configuration clock
617 - const: bus_master # Master AXI clock
618 - const: bus_slave # Slave AXI clock
619 - const: slave_q2a # Slave Q2A clock
620 - const: ddrss_sf_tbu # PCIe SF TBU clock
621 - const: aggre0 # Aggre NoC PCIe0 AXI clock
622 - const: aggre1 # Aggre NoC PCIe1 AXI clock
627 - const: pci # PCIe core reset
634 - qcom,pcie-sm8450-pcie1
642 - const: pipe # PIPE clock
643 - const: pipe_mux # PIPE MUX
644 - const: phy_pipe # PIPE output clock
645 - const: ref # REFERENCE clock
646 - const: aux # Auxiliary clock
647 - const: cfg # Configuration clock
648 - const: bus_master # Master AXI clock
649 - const: bus_slave # Slave AXI clock
650 - const: slave_q2a # Slave Q2A clock
651 - const: ddrss_sf_tbu # PCIe SF TBU clock
652 - const: aggre1 # Aggre NoC PCIe1 AXI clock
657 - const: pci # PCIe core reset
673 - const: aux # Auxiliary clock
674 - const: cfg # Configuration clock
675 - const: bus_master # Master AXI clock
676 - const: bus_slave # Slave AXI clock
677 - const: slave_q2a # Slave Q2A clock
678 - const: ddrss_sf_tbu # PCIe SF TBU clock
679 - const: noc_aggr # Aggre NoC PCIe AXI clock
680 - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock
687 - const: pci # PCIe core reset
688 - const: link_down # PCIe link down reset
705 - const: aux # Auxiliary clock
706 - const: cfg # Configuration clock
707 - const: bus_master # Master AXI clock
708 - const: bus_slave # Slave AXI clock
709 - const: slave_q2a # Slave Q2A clock
710 - const: ddrss_sf_tbu # PCIe SF TBU clock
711 - const: noc_aggr_4 # NoC aggregate 4 clock
712 - const: noc_aggr_south_sf # NoC aggregate South SF clock
713 - const: cnoc_qx # Configuration NoC QX clock
718 - const: pci # PCIe core reset
733 - const: pipe # PIPE clock
734 - const: aux # Auxiliary clock
735 - const: cfg # Configuration clock
736 - const: bus_master # Master AXI clock
737 - const: bus_slave # Slave AXI clock
738 - const: slave_q2a # Slave Q2A clock
739 - const: sleep # PCIe Sleep clock
744 - const: pci # PCIe core reset
767 - qcom,pcie-ipq8064v2
769 - qcom,pcie-ipq8074-gen3
799 - qcom,pcie-sm8450-pcie0
800 - qcom,pcie-sm8450-pcie1
852 - qcom,pcie-ipq8064-v2
854 - qcom,pcie-ipq8074-gen3
865 unevaluatedProperties: false
869 #include <dt-bindings/interrupt-controller/arm-gic.h>
871 compatible = "qcom,pcie-ipq8064";
872 reg = <0x1b500000 0x1000>,
875 <0x0ff00000 0x100000>;
876 reg-names = "dbi", "elbi", "parf", "config";
878 linux,pci-domain = <0>;
879 bus-range = <0x00 0xff>;
881 #address-cells = <3>;
883 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>,
884 <0x82000000 0 0 0x08000000 0 0x07e00000>;
885 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
886 interrupt-names = "msi";
887 #interrupt-cells = <1>;
888 interrupt-map-mask = <0 0 0 0x7>;
889 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>,
890 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>,
891 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>,
892 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>;
898 clock-names = "core", "iface", "phy", "aux", "ref";
905 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
906 pinctrl-0 = <&pcie_pins_default>;
907 pinctrl-names = "default";
908 vdda-supply = <&pm8921_s3>;
909 vdda_phy-supply = <&pm8921_lvs6>;
910 vdda_refclk-supply = <&ext_3p3v>;
913 #include <dt-bindings/interrupt-controller/arm-gic.h>
914 #include <dt-bindings/gpio/gpio.h>
916 compatible = "qcom,pcie-apq8084";
917 reg = <0xfc520000 0x2000>,
921 reg-names = "parf", "dbi", "elbi", "config";
923 linux,pci-domain = <0>;
924 bus-range = <0x00 0xff>;
926 #address-cells = <3>;
928 ranges = <0x81000000 0 0 0xff200000 0 0x00100000>,
929 <0x82000000 0 0x00300000 0xff300000 0 0x00d00000>;
930 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
931 interrupt-names = "msi";
932 #interrupt-cells = <1>;
933 interrupt-map-mask = <0 0 0 0x7>;
934 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>,
935 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>,
936 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>,
937 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>;
942 clock-names = "iface", "master_bus", "slave_bus", "aux";
944 reset-names = "core";
945 power-domains = <&gcc 1>;
946 vdda-supply = <&pma8084_l3>;
948 phy-names = "pciephy";
949 perst-gpios = <&tlmm 70 GPIO_ACTIVE_LOW>;
950 pinctrl-0 = <&pcie0_pins_default>;
951 pinctrl-names = "default";