1 * Qualcomm PCI express root complex
5 Value type: <stringlist>
6 Definition: Value should contain
7 - "qcom,pcie-ipq8064" for ipq8064
8 - "qcom,pcie-apq8064" for apq8064
9 - "qcom,pcie-apq8084" for apq8084
10 - "qcom,pcie-msm8996" for msm8996 or apq8096
11 - "qcom,pcie-ipq4019" for ipq4019
12 - "qcom,pcie-ipq8074" for ipq8074
13 - "qcom,pcie-qcs404" for qcs404
17 Value type: <prop-encoded-array>
18 Definition: Register ranges as listed in the reg-names property
22 Value type: <stringlist>
23 Definition: Must include the following entries
24 - "parf" Qualcomm specific registers
25 - "dbi" DesignWare PCIe registers
26 - "elbi" External local bus interface registers
27 - "config" PCIe configuration space
32 Definition: Should be "pci". As specified in designware-pcie.txt
37 Definition: Should be 3. As specified in designware-pcie.txt
42 Definition: Should be 2. As specified in designware-pcie.txt
46 Value type: <prop-encoded-array>
47 Definition: As specified in designware-pcie.txt
51 Value type: <prop-encoded-array>
52 Definition: MSI interrupt
56 Value type: <stringlist>
57 Definition: Should contain "msi"
62 Definition: Should be 1. As specified in designware-pcie.txt
66 Value type: <prop-encoded-array>
67 Definition: As specified in designware-pcie.txt
71 Value type: <prop-encoded-array>
72 Definition: As specified in designware-pcie.txt
76 Value type: <prop-encoded-array>
77 Definition: List of phandle and clock specifier pairs as listed
78 in clock-names property
82 Value type: <stringlist>
83 Definition: Should contain the following entries
84 - "iface" Configuration AHB clock
87 Usage: required for ipq/apq8064
88 Value type: <stringlist>
89 Definition: Should contain the following entries
90 - "core" Clocks the pcie hw block
91 - "phy" Clocks the pcie PHY block
93 Usage: required for apq8084/ipq4019
94 Value type: <stringlist>
95 Definition: Should contain the following entries
96 - "aux" Auxiliary (AUX) clock
97 - "bus_master" Master AXI clock
98 - "bus_slave" Slave AXI clock
101 Usage: required for msm8996/apq8096
102 Value type: <stringlist>
103 Definition: Should contain the following entries
104 - "pipe" Pipe Clock driving internal logic
105 - "aux" Auxiliary (AUX) clock
106 - "cfg" Configuration clock
107 - "bus_master" Master AXI clock
108 - "bus_slave" Slave AXI clock
111 Usage: required for ipq8074
112 Value type: <stringlist>
113 Definition: Should contain the following entries
114 - "iface" PCIe to SysNOC BIU clock
115 - "axi_m" AXI Master clock
116 - "axi_s" AXI Slave clock
118 - "aux" Auxiliary clock
121 Usage: required for qcs404
122 Value type: <stringlist>
123 Definition: Should contain the following entries
125 - "aux" Auxiliary clock
126 - "master_bus" AXI Master clock
127 - "slave_bus" AXI Slave clock
131 Value type: <prop-encoded-array>
132 Definition: List of phandle and reset specifier pairs as listed
133 in reset-names property
136 Usage: required for ipq/apq8064
137 Value type: <stringlist>
138 Definition: Should contain the following entries
146 Usage: required for apq8084
147 Value type: <stringlist>
148 Definition: Should contain the following entries
152 Usage: required for ipq/apq8064
153 Value type: <stringlist>
154 Definition: Should contain the following entries
155 - "axi_m" AXI master reset
156 - "axi_s" AXI slave reset
158 - "axi_m_vmid" VMID reset
159 - "axi_s_xpu" XPU reset
162 - "axi_m_sticky" AXI sticky reset
163 - "pipe_sticky" PIPE sticky reset
166 - "phy_ahb" PHY AHB reset
169 Usage: required for ipq8074
170 Value type: <stringlist>
171 Definition: Should contain the following entries
173 - "sleep" Sleep reset
174 - "sticky" Core Sticky reset
175 - "axi_m" AXI Master reset
176 - "axi_s" AXI Slave reset
178 - "axi_m_sticky" AXI Master Sticky reset
181 Usage: required for qcs404
182 Value type: <stringlist>
183 Definition: Should contain the following entries
184 - "axi_m" AXI Master reset
185 - "axi_s" AXI Slave reset
186 - "axi_m_sticky" AXI Master Sticky reset
187 - "pipe_sticky" PIPE sticky reset
192 Usage: required for apq8084 and msm8996/apq8096
193 Value type: <prop-encoded-array>
194 Definition: A phandle and power domain specifier pair to the
195 power domain which is responsible for collapsing
196 and restoring power to the peripheral
200 Value type: <phandle>
201 Definition: A phandle to the core analog power supply
204 Usage: required for ipq/apq8064
205 Value type: <phandle>
206 Definition: A phandle to the analog power supply for PHY
208 - vdda_refclk-supply:
209 Usage: required for ipq/apq8064
210 Value type: <phandle>
211 Definition: A phandle to the analog power supply for IC which generates
215 Value type: <phandle>
216 Definition: A phandle to the PCIe endpoint power supply
219 Usage: required for apq8084 and qcs404
220 Value type: <phandle>
221 Definition: List of phandle(s) as listed in phy-names property
224 Usage: required for apq8084 and qcs404
225 Value type: <stringlist>
226 Definition: Should contain "pciephy"
230 Value type: <prop-encoded-array>
231 Definition: List of phandle and GPIO specifier pairs. Should contain
232 - "perst-gpios" PCIe endpoint reset signal line
233 - "wake-gpios" PCIe endpoint wake signal line
235 * Example for ipq/apq8064
237 compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie";
238 reg = <0x1b500000 0x1000
241 0x0ff00000 0x100000>;
242 reg-names = "dbi", "elbi", "parf", "config";
244 linux,pci-domain = <0>;
245 bus-range = <0x00 0xff>;
247 #address-cells = <3>;
249 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
250 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
251 interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
252 interrupt-names = "msi";
253 #interrupt-cells = <1>;
254 interrupt-map-mask = <0 0 0 0x7>;
255 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
256 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
257 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
258 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
259 clocks = <&gcc PCIE_A_CLK>,
262 clock-names = "core", "iface", "phy";
263 resets = <&gcc PCIE_ACLK_RESET>,
264 <&gcc PCIE_HCLK_RESET>,
265 <&gcc PCIE_POR_RESET>,
266 <&gcc PCIE_PCI_RESET>,
267 <&gcc PCIE_PHY_RESET>;
268 reset-names = "axi", "ahb", "por", "pci", "phy";
269 pinctrl-0 = <&pcie_pins_default>;
270 pinctrl-names = "default";
273 * Example for apq8084
275 compatible = "qcom,pcie-apq8084", "snps,dw-pcie";
276 reg = <0xfc520000 0x2000>,
280 reg-names = "parf", "dbi", "elbi", "config";
282 linux,pci-domain = <0>;
283 bus-range = <0x00 0xff>;
285 #address-cells = <3>;
287 ranges = <0x81000000 0 0 0xff200000 0 0x00100000 /* I/O */
288 0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; /* memory */
289 interrupts = <GIC_SPI 243 IRQ_TYPE_NONE>;
290 interrupt-names = "msi";
291 #interrupt-cells = <1>;
292 interrupt-map-mask = <0 0 0 0x7>;
293 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
294 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
295 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
296 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
297 clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
298 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
299 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
300 <&gcc GCC_PCIE_0_AUX_CLK>;
301 clock-names = "iface", "master_bus", "slave_bus", "aux";
302 resets = <&gcc GCC_PCIE_0_BCR>;
303 reset-names = "core";
304 power-domains = <&gcc PCIE0_GDSC>;
305 vdda-supply = <&pma8084_l3>;
307 phy-names = "pciephy";
308 perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>;
309 pinctrl-0 = <&pcie0_pins_default>;
310 pinctrl-names = "default";