Documentation/devicetree/bindings/pci/qcom,pcie-sc8280xp.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sc8280xp.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm SC8280XP PCI Express Root Complex
   8
   9 maintainers:
  10   - Bjorn Andersson <andersson@kernel.org>
  11   - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  12
  13 description:
  14   Qualcomm SC8280XP SoC PCIe root complex controller is based on the Synopsys
  15   DesignWare PCIe IP.
  16
  17 properties:
  18   compatible:
  19     enum:
  20       - qcom,pcie-sa8540p
  21       - qcom,pcie-sc8280xp
  22
  23   reg:
  24     minItems: 5
  25     maxItems: 6
  26
  27   reg-names:
  28     minItems: 5
  29     items:
  30       - const: parf # Qualcomm specific registers
  31       - const: dbi # DesignWare PCIe registers
  32       - const: elbi # External local bus interface registers
  33       - const: atu # ATU address space
  34       - const: config # PCIe configuration space
  35       - const: mhi # MHI registers
  36
  37   clocks:
  38     minItems: 8
  39     maxItems: 9
  40
  41   clock-names:
  42     minItems: 8
  43     items:
  44       - const: aux # Auxiliary clock
  45       - const: cfg # Configuration clock
  46       - const: bus_master # Master AXI clock
  47       - const: bus_slave # Slave AXI clock
  48       - const: slave_q2a # Slave Q2A clock
  49       - const: ddrss_sf_tbu # PCIe SF TBU clock
  50       - const: noc_aggr_4 # NoC aggregate 4 clock
  51       - const: noc_aggr_south_sf # NoC aggregate South SF clock
  52       - const: cnoc_qx # Configuration NoC QX clock
  53
  54   resets:
  55     maxItems: 1
  56
  57   reset-names:
  58     items:
  59       - const: pci
  60
  61   vddpe-3v3-supply:
  62     description: A phandle to the PCIe endpoint power supply
  63
  64 required:
  65   - interconnects
  66   - interconnect-names
  67
  68 allOf:
  69   - $ref: qcom,pcie-common.yaml#
  70   - if:
  71       properties:
  72         compatible:
  73           contains:
  74             enum:
  75               - qcom,pcie-sc8280xp
  76     then:
  77       properties:
  78         interrupts:
  79           minItems: 4
  80           maxItems: 4
  81         interrupt-names:
  82           items:
  83             - const: msi0
  84             - const: msi1
  85             - const: msi2
  86             - const: msi3
  87     else:
  88       properties:
  89         interrupts:
  90           maxItems: 1
  91         interrupt-names:
  92           items:
  93             - const: msi
  94
  95 unevaluatedProperties: false
  96
  97 examples:
  98   - |
  99     #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
 100     #include <dt-bindings/gpio/gpio.h>
 101     #include <dt-bindings/interconnect/qcom,sc8280xp.h>
 102     #include <dt-bindings/interrupt-controller/arm-gic.h>
 103
 104     soc {
 105         #address-cells = <2>;
 106         #size-cells = <2>;
 107
 108         pcie@1c20000 {
 109             compatible = "qcom,pcie-sc8280xp";
 110             reg = <0x0 0x01c20000 0x0 0x3000>,
 111                   <0x0 0x3c000000 0x0 0xf1d>,
 112                   <0x0 0x3c000f20 0x0 0xa8>,
 113                   <0x0 0x3c001000 0x0 0x1000>,
 114                   <0x0 0x3c100000 0x0 0x100000>,
 115                   <0x0 0x01c23000 0x0 0x1000>;
 116             reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
 117             ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>,
 118                      <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>;
 119
 120             bus-range = <0x00 0xff>;
 121             device_type = "pci";
 122             linux,pci-domain = <2>;
 123             num-lanes = <4>;
 124
 125             #address-cells = <3>;
 126             #size-cells = <2>;
 127
 128             assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>;
 129             assigned-clock-rates = <19200000>;
 130             clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
 131                      <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
 132                      <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>,
 133                      <&gcc GCC_PCIE_2A_SLV_AXI_CLK>,
 134                      <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>,
 135                      <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
 136                      <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
 137                      <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
 138             clock-names = "aux",
 139                           "cfg",
 140                           "bus_master",
 141                           "bus_slave",
 142                           "slave_q2a",
 143                           "ddrss_sf_tbu",
 144                           "noc_aggr_4",
 145                           "noc_aggr_south_sf";
 146
 147             dma-coherent;
 148
 149             interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
 150                          <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
 151                          <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
 152                          <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>;
 153             interrupt-names = "msi0", "msi1", "msi2", "msi3";
 154             #interrupt-cells = <1>;
 155             interrupt-map-mask = <0 0 0 0x7>;
 156             interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
 157                             <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
 158                             <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
 159                             <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
 160
 161             interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>,
 162                             <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>;
 163             interconnect-names = "pcie-mem", "cpu-pcie";
 164
 165             phys = <&pcie2a_phy>;
 166             phy-names = "pciephy";
 167
 168             pinctrl-0 = <&pcie2a_default>;
 169             pinctrl-names = "default";
 170
 171             power-domains = <&gcc PCIE_2A_GDSC>;
 172
 173             resets = <&gcc GCC_PCIE_2A_BCR>;
 174             reset-names = "pci";
 175
 176             perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
 177             wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
 178             vddpe-3v3-supply = <&vreg_nvme>;
 179         };
 180     };