Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sc7280.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm SC7280 PCI Express Root Complex
   8
   9 maintainers:
  10   - Bjorn Andersson <andersson@kernel.org>
  11   - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  12
  13 description:
  14   Qualcomm SC7280 SoC PCIe root complex controller is based on the Synopsys
  15   DesignWare PCIe IP.
  16
  17 properties:
  18   compatible:
  19     const: qcom,pcie-sc7280
  20
  21   reg:
  22     minItems: 5
  23     maxItems: 6
  24
  25   reg-names:
  26     minItems: 5
  27     items:
  28       - const: parf # Qualcomm specific registers
  29       - const: dbi # DesignWare PCIe registers
  30       - const: elbi # External local bus interface registers
  31       - const: atu # ATU address space
  32       - const: config # PCIe configuration space
  33       - const: mhi # MHI registers
  34
  35   clocks:
  36     minItems: 13
  37     maxItems: 13
  38
  39   clock-names:
  40     items:
  41       - const: pipe # PIPE clock
  42       - const: pipe_mux # PIPE MUX
  43       - const: phy_pipe # PIPE output clock
  44       - const: ref # REFERENCE clock
  45       - const: aux # Auxiliary clock
  46       - const: cfg # Configuration clock
  47       - const: bus_master # Master AXI clock
  48       - const: bus_slave # Slave AXI clock
  49       - const: slave_q2a # Slave Q2A clock
  50       - const: tbu # PCIe TBU clock
  51       - const: ddrss_sf_tbu # PCIe SF TBU clock
  52       - const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock
  53       - const: aggre1 # Aggre NoC PCIe1 AXI clock
  54
  55   interrupts:
  56     maxItems: 1
  57
  58   interrupt-names:
  59     items:
  60       - const: msi
  61
  62   resets:
  63     maxItems: 1
  64
  65   reset-names:
  66     items:
  67       - const: pci
  68
  69   vddpe-3v3-supply:
  70     description: PCIe endpoint power supply
  71
  72 allOf:
  73   - $ref: qcom,pcie-common.yaml#
  74
  75 unevaluatedProperties: false
  76
  77 examples:
  78   - |
  79     #include <dt-bindings/clock/qcom,gcc-sc7280.h>
  80     #include <dt-bindings/clock/qcom,rpmh.h>
  81     #include <dt-bindings/gpio/gpio.h>
  82     #include <dt-bindings/interrupt-controller/arm-gic.h>
  83
  84     soc {
  85         #address-cells = <2>;
  86         #size-cells = <2>;
  87
  88         pcie@1c08000 {
  89             compatible = "qcom,pcie-sc7280";
  90             reg = <0 0x01c08000 0 0x3000>,
  91                   <0 0x40000000 0 0xf1d>,
  92                   <0 0x40000f20 0 0xa8>,
  93                   <0 0x40001000 0 0x1000>,
  94                   <0 0x40100000 0 0x100000>;
  95             reg-names = "parf", "dbi", "elbi", "atu", "config";
  96             ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
  97                      <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
  98
  99             bus-range = <0x00 0xff>;
 100             device_type = "pci";
 101             linux,pci-domain = <1>;
 102             num-lanes = <2>;
 103
 104             #address-cells = <3>;
 105             #size-cells = <2>;
 106
 107             assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
 108             assigned-clock-rates = <19200000>;
 109
 110             clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
 111                      <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
 112                      <&pcie1_phy>,
 113                      <&rpmhcc RPMH_CXO_CLK>,
 114                      <&gcc GCC_PCIE_1_AUX_CLK>,
 115                      <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
 116                      <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
 117                      <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
 118                      <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
 119                      <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
 120                      <&gcc GCC_DDRSS_PCIE_SF_CLK>,
 121                      <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>,
 122                      <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
 123
 124             clock-names = "pipe",
 125                           "pipe_mux",
 126                           "phy_pipe",
 127                           "ref",
 128                           "aux",
 129                           "cfg",
 130                           "bus_master",
 131                           "bus_slave",
 132                           "slave_q2a",
 133                           "tbu",
 134                           "ddrss_sf_tbu",
 135                           "aggre0",
 136                           "aggre1";
 137
 138             dma-coherent;
 139
 140             interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
 141             interrupt-names = "msi";
 142             #interrupt-cells = <1>;
 143             interrupt-map-mask = <0 0 0 0x7>;
 144             interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
 145                             <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>,
 146                             <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,
 147                             <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;
 148
 149             iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
 150                         <0x100 &apps_smmu 0x1c81 0x1>;
 151
 152             phys = <&pcie1_phy>;
 153             phy-names = "pciephy";
 154
 155             pinctrl-names = "default";
 156             pinctrl-0 = <&pcie1_clkreq_n>;
 157
 158             power-domains = <&gcc GCC_PCIE_1_GDSC>;
 159
 160             resets = <&gcc GCC_PCIE_1_BCR>;
 161             reset-names = "pci";
 162
 163             perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
 164             vddpe-3v3-supply = <&pp3300_ssd>;
 165         };
 166     };