1 NVIDIA Tegra PCIe controller (Synopsys DesignWare Core based)
3 This PCIe controller is based on the Synopsis Designware PCIe IP
4 and thus inherits all the common properties defined in snps,dw-pcie.yaml and
6 Some of the controller instances are dual mode where in they can work either
7 in root port mode or endpoint mode but one at a time.
10 - power-domains: A phandle to the node that controls power to the respective
11 PCIe controller and a specifier name for the PCIe controller. Following are
12 the specifiers for the different PCIe controllers
13 TEGRA194_POWER_DOMAIN_PCIEX8B: C0
14 TEGRA194_POWER_DOMAIN_PCIEX1A: C1
15 TEGRA194_POWER_DOMAIN_PCIEX1A: C2
16 TEGRA194_POWER_DOMAIN_PCIEX1A: C3
17 TEGRA194_POWER_DOMAIN_PCIEX4A: C4
18 TEGRA194_POWER_DOMAIN_PCIEX8A: C5
19 these specifiers are defined in
20 "include/dt-bindings/power/tegra194-powergate.h" file.
21 - reg: A list of physical base address and length pairs for each set of
22 controller registers. Must contain an entry for each entry in the reg-names
24 - reg-names: Must include the following entries:
25 "appl": Controller's application logic registers
26 "config": As per the definition in snps,dw-pcie.yaml
27 "atu_dma": iATU and DMA registers. This is where the iATU (internal Address
28 Translation Unit) registers of the PCIe core are made available
30 "dbi": The aperture where root port's own configuration registers are
32 - interrupts: A list of interrupt outputs of the controller. Must contain an
33 entry for each entry in the interrupt-names property.
34 - interrupt-names: Must include the following entries:
35 "intr": The Tegra interrupt that is asserted for controller interrupts
36 - clocks: Must contain an entry for each entry in clock-names.
37 See ../clocks/clock-bindings.txt for details.
38 - clock-names: Must include the following entries:
40 - resets: Must contain an entry for each entry in reset-names.
41 See ../reset/reset.txt for details.
42 - reset-names: Must include the following entries:
45 - phys: Must contain a phandle to P2U PHY for each entry in phy-names.
46 - phy-names: Must include an entry for each active lane.
47 "p2u-N": where N ranges from 0 to one less than the total number of lanes
48 - nvidia,bpmp: Must contain a pair of phandle to BPMP controller node followed
49 by controller-id. Following are the controller ids for each controller.
56 - vddio-pex-ctl-supply: Regulator supply for PCIe side band signals
59 - compatible: Tegra19x must contain "nvidia,tegra194-pcie"
60 - device_type: Must be "pci" for RC mode
61 - interrupt-names: Must include the following entries:
62 "msi": The Tegra interrupt that is asserted when an MSI is received
63 - bus-range: Range of bus numbers associated with this controller
64 - #address-cells: Address representation for root ports (must be 3)
65 - cell 0 specifies the bus and device numbers of the root port:
67 [15:11]: device number
68 - cell 1 denotes the upper 32 address bits and should be 0
69 - cell 2 contains the lower 32 address bits and is used to translate to the
71 - #size-cells: Size representation for root ports (must be 2)
72 - ranges: Describes the translation of addresses for root ports and standard
73 PCI regions. The entries must be 7 cells each, where the first three cells
74 correspond to the address as described for the #address-cells property
75 above, the fourth and fifth cells are for the physical CPU address to
76 translate to and the sixth and seventh cells are as described for the
77 #size-cells property above.
78 - Entries setup the mapping for the standard I/O, memory and
79 prefetchable PCI regions. The first cell determines the type of region
81 - 0x81000000: I/O memory region
82 - 0x82000000: non-prefetchable memory region
83 - 0xc2000000: prefetchable memory region
84 Please refer to the standard PCI bus binding document for a more detailed
86 - #interrupt-cells: Size representation for interrupts (must be 1)
87 - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
88 Please refer to the standard PCI bus binding document for a more detailed
92 In Tegra194, Only controllers C0, C4 & C5 support EP mode.
93 - compatible: Tegra19x must contain "nvidia,tegra194-pcie-ep"
94 - reg-names: Must include the following entries:
95 "addr_space": Used to map remote RC address space
96 - reset-gpios: Must contain a phandle to a GPIO controller followed by
97 GPIO that is being used as PERST input signal. Please refer to pci.txt
101 - pinctrl-names: A list of pinctrl state names.
102 It is mandatory for C5 controller and optional for other controllers.
103 - "default": Configures PCIe I/O for proper operation.
104 - pinctrl-0: phandle for the 'default' state of pin configuration.
105 It is mandatory for C5 controller and optional for other controllers.
106 - supports-clkreq: Refer to Documentation/devicetree/bindings/pci/pci.txt
107 - nvidia,update-fc-fixup: This is a boolean property and needs to be present to
108 improve performance when a platform is designed in such a way that it
109 satisfies at least one of the following conditions thereby enabling root
110 port to exchange optimum number of FC (Flow Control) credits with
112 1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
113 2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
114 a) speed is Gen-2 and MPS is 256B
115 b) speed is >= Gen-3 with any MPS
116 - nvidia,aspm-cmrt-us: Common Mode Restore Time for proper operation of ASPM
117 to be specified in microseconds
118 - nvidia,aspm-pwr-on-t-us: Power On time for proper operation of ASPM to be
119 specified in microseconds
120 - nvidia,aspm-l0s-entrance-latency-us: ASPM L0s entrance latency to be
121 specified in microseconds
124 - vpcie3v3-supply: A phandle to the regulator node that supplies 3.3V to the slot
125 if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
126 in p2972-0000 platform).
127 - vpcie12v-supply: A phandle to the regulator node that supplies 12V to the slot
128 if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
129 in p2972-0000 platform).
132 - nvidia,refclk-select-gpios: Must contain a phandle to a GPIO controller
133 followed by GPIO that is being used to enable REFCLK to controller from host
135 NOTE:- On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
136 operate in the endpoint mode because of the way the platform is designed.
145 compatible = "nvidia,tegra194-pcie";
146 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
147 reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
148 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */
149 0x00 0x38040000 0x0 0x00040000>; /* iATU_DMA reg space (256K) */
150 reg-names = "appl", "config", "atu_dma";
152 #address-cells = <3>;
156 linux,pci-domain = <0>;
158 pinctrl-names = "default";
159 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
161 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
162 clock-names = "core";
164 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
165 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
166 reset-names = "apb", "core";
168 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
169 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
170 interrupt-names = "intr", "msi";
172 #interrupt-cells = <1>;
173 interrupt-map-mask = <0 0 0 0>;
174 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
176 nvidia,bpmp = <&bpmp 0>;
179 nvidia,aspm-cmrt-us = <60>;
180 nvidia,aspm-pwr-on-t-us = <20>;
181 nvidia,aspm-l0s-entrance-latency-us = <3>;
183 bus-range = <0x0 0xff>;
184 ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */
185 0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01E00000 /* non-prefetchable memory (30MB) */
186 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory (16GB) */
188 vddio-pex-ctl-supply = <&vdd_1v8ao>;
189 vpcie3v3-supply = <&vdd_3v3_pcie>;
190 vpcie12v-supply = <&vdd_12v_pcie>;
192 phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>,
194 phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
201 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
202 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
203 reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
204 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
205 0x00 0x3a080000 0x0 0x00040000 /* DBI reg space (256K) */
206 0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
207 reg-names = "appl", "atu_dma", "dbi", "addr_space";
210 num-ib-windows = <2>;
211 num-ob-windows = <8>;
213 pinctrl-names = "default";
214 pinctrl-0 = <&clkreq_c5_bi_dir_state>;
216 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
217 clock-names = "core";
219 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
220 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
221 reset-names = "apb", "core";
223 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
224 interrupt-names = "intr";
226 nvidia,bpmp = <&bpmp 5>;
228 nvidia,aspm-cmrt-us = <60>;
229 nvidia,aspm-pwr-on-t-us = <20>;
230 nvidia,aspm-l0s-entrance-latency-us = <3>;
232 vddio-pex-ctl-supply = <&vdd_1v8ao>;
234 reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>;
236 nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5)
239 phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
240 <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
241 <&p2u_nvhs_6>, <&p2u_nvhs_7>;
243 phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
244 "p2u-5", "p2u-6", "p2u-7";